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21. 发明申请

US20140223210A1 Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Distribution 有权
标题翻译：用于宽带宽共振全局时钟分配的可调谐扇区缓冲区
公开(公告)号：US20140223210A1
公开(公告)日：2014-08-07
申请号：US13759646
申请日：2013-02-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G.R. Thomson
IPC分类号： G06F1/10 , G06F1/32
CPC分类号： G06F1/10 , G06F1/324 , Y02D10/126
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.
摘要翻译：宽带谐振时钟分布包括被配置为将时钟信号分配给集成电路的多个分量的时钟网格和被配置为接收时钟信号并向时钟网格提供输出的可调谐扇区缓冲器。可调谐扇区缓冲器被配置为基于所识别的谐振或非谐振模式来设置时钟信号的延迟和转换速率。

22. 发明授权

US09779869B2 High efficiency on-chip 3D transformer structure 有权
公开(公告)号：US09779869B2
公开(公告)日：2017-10-03
申请号：US13950557
申请日：2013-07-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Robert L. Barry , Robert A. Groves , Venkata Nr. Vanukuru
IPC分类号： H01F5/00 , H01F27/28 , H01F7/06
CPC分类号： H01F27/2804 , H01F27/2871 , H01F2027/2809 , Y10T29/49071
摘要： An integrated circuit transformer structure includes at least two conductor groups stacked in parallel in different layers. A first spiral track is formed in the at least two conductor groups, the first spiral track included first turns of a first radius within each of the at least two conductor groups, and second turns of a second radius within each of the at least two conductor groups, the first and second turns being electrically connected. A second spiral track is formed in the at least two conductor groups, the second spiral track including third turns of a third radius within each of the at least two conductor groups and disposed in a same plane between the first and second turns in each of the at least two conductor groups.

23. 发明申请

US20150364241A1 SOLENOIDAL SERIES STACKED MULTIPATH INDUCTOR 有权
标题翻译：电磁串联堆叠多路电感
公开(公告)号：US20150364241A1
公开(公告)日：2015-12-17
申请号：US14304564
申请日：2014-06-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Robert A. Groves , Venkata Nr. Vanukuru
IPC分类号： H01F27/28 , H01F41/04 , H01F41/10
CPC分类号： H01F41/041 , H01F17/0033 , H01F2017/0053
摘要： A series stacked, solenoidally wound, multipath inductor includes a plurality of turns disposed about a center region on two layers. The turns on the two layers have corresponding geometry therebetween. Each of the plurality of turns includes two or more segments that extend length-wise along the turns. The segments have positions that vary from an innermost position relative to the center region and an outermost position relative to the center region. A cross-over architecture is configured to couple the segments of a turn on one layer with the segments on a turn on another layer to form segment paths that have a substantially same length for all segment paths in a segment path grouping between the two layers.
摘要翻译：串联堆叠的，电磁绕组的多路径电感器包括围绕两层的中心区域设置的多个匝。两层之间的转动在它们之间具有对应的几何形状。多个匝中的每一个包括两个或更多个沿匝延伸的段。这些段具有从相对于中心区域的最内部位置和相对于中心区域的最外侧位置变化的位置。交叉架构被配置为将一层上的转弯的段与另一层上的转弯上的段耦合，以形成对于在两个层之间分组的段路径中的所有段路径具有基本相同的长度的段路径。

24. 发明授权

US09171663B2 High efficiency on-chip 3D transformer structure 有权
标题翻译：高效率片上3D变压器结构
公开(公告)号：US09171663B2
公开(公告)日：2015-10-27
申请号：US13950947
申请日：2013-07-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Robert L. Barry , Robert A. Groves , Venkata Nr. Vanukuru
IPC分类号： H01F5/00 , H01F27/28 , H01L27/08
CPC分类号： H01F27/2804 , H01F27/2871 , H01F2027/2809
摘要： An integrated circuit transformer structure includes at least two conductor groups stacked in parallel in different layers. A first spiral track is formed in the at least two conductor groups, the first spiral track includes first turns of a first radius within each of the at least two conductor groups, and second turns of a second radius within each of the at least two conductor groups, the first and second turns being electrically connected. A second spiral track is formed in the at least two conductor groups, the second spiral track including a plurality of adjacent turns of one or more radii within each of the at least two conductor groups and disposed in a same plane between the first and second turns in each of the at least two conductor groups.
摘要翻译：集成电路变压器结构包括在不同层中并联堆叠的至少两个导体组。在所述至少两个导体组中形成第一螺旋形轨道，所述第一螺旋轨道包括所述至少两个导体组中每一个内的第一半径的第一匝，以及所述至少两个导体的每一个内的第二半径的第二匝组，第一和第二匝电连接。在所述至少两个导体组中形成第二螺旋轨道，所述第二螺旋轨道包括在所述至少两个导体组中的每一个内的一个或多个半径的多个相邻匝，并且设置在所述第一和第二匝之间的同一平面中在至少两个导体组中的每一个中。

25. 发明申请

US20140218087A1 Wide Bandwidth Resonant Global Clock Distribution 有权
标题翻译：宽带宽共振全局时钟分配
公开(公告)号：US20140218087A1
公开(公告)日：2014-08-07
申请号：US13759311
申请日：2013-02-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G.R. Thomson
IPC分类号： H03K5/06
CPC分类号： H03K5/06 , G06F1/10
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.
摘要翻译：宽带谐振时钟分配包括被配置为将时钟信号分配给集成电路的多个分量的时钟网格，配置成接收时钟信号并向时钟网格提供输出的可调谐扇区缓冲器，至少一个电感器，至少一个可调谐电阻开关和电容器网络。可调谐扇区缓冲器可编程设置时钟信号的延时和转换速率。电感，可调电阻开关和电容网络连接在时钟网格和参考电压之间。所述至少一个可调谐电阻开关是可编程的，以基于所述时钟信号的频率，将所述至少一个电感器动态地切换到所述时钟分布中或者从所述时钟分布中产生至少一个谐振模式或非谐振模式。

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