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21. 发明申请

US20210011645A1 CIRCUIT PARTITIONING FOR A MEMORY DEVICE 有权
公开(公告)号：US20210011645A1
公开(公告)日：2021-01-14
申请号：US16508729
申请日：2019-07-11
申请人： Micron Technology, Inc.
发明人： Andrea Martinelli , Christophe Vincent Antoine Laurent , Claudio Nava , Marco Defendi
IPC分类号： G06F3/06 , G11C11/22 , G11C11/408 , G11C11/4091 , G06F11/10 , G11C29/52
摘要： Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.

22. 发明授权

US10510407B2 Efficient utilization of memory die area 有权
公开(公告)号：US10510407B2
公开(公告)日：2019-12-17
申请号：US16405617
申请日：2019-05-07
申请人： Micron Technology, Inc.
发明人： Christophe Vincent Antoine Laurent
IPC分类号： G11C5/02 , G11C5/06 , G11C13/00
摘要： Methods, systems, and apparatus that support efficient utilization of die area for cross-point memory architecture are described. A memory array may include active memory cells overlying each portion of the substrate that includes certain types of support circuitry, such as decoders and sense amplifiers. Boundary tiles, which may be portions of an array having a different configuration from other portions of the array, may be positioned on one side of an array of memory tiles. The boundary tiles may include support components to access both memory cells of neighboring memory tiles and memory cells overlying the boundary tiles. Column lines and column line decoders may be integrated as part of a boundary tile. Access lines, such as row lines may be truncated or omitted at or near borders of the memory portion of the memory device.

23. 发明申请

US20190103139A1 ACTIVE BOUNDARY QUILT ARCHITECTURE MEMORY 审中-公开
公开(公告)号：US20190103139A1
公开(公告)日：2019-04-04
申请号：US16189447
申请日：2018-11-13
申请人： Micron Technology, Inc.
发明人： Christophe Vincent Antoine Laurent
IPC分类号： G11C5/02 , H01L27/24 , H01L45/00 , H01L27/02 , G11C8/10
摘要： Methods, systems, and apparatus that increase available memory or storage using active boundary areas in quilt architecture are described. A memory array may include memory cells overlying each portion of a substrate layer that includes certain types of support circuitry, such as decoders and sense amplifiers. Active boundary portions, which may be elements of the memory array having a different configuration from other portions of the memory array, may be positioned on two sides of the memory array and may increase available data in a quilt architecture memory. The active boundary portions may include support components to access both memory cells of neighboring memory portions and memory cells overlying the active boundary portions. Address scrambling may produce a uniform increase in number of available data in conjunction with the active boundary portions.

24. 发明申请

US20150341033A1 APPARATUS AND METHODS FOR LEAKAGE CURRENT REDUCTION IN INTEGRATED CIRCUITS 有权
标题翻译：集成电路中漏电流减少的装置和方法
公开(公告)号：US20150341033A1
公开(公告)日：2015-11-26
申请号：US14814852
申请日：2015-07-31
申请人： MICRON TECHNOLOGY, INC.
发明人： Christophe Vincent Antoine Laurent
IPC分类号： H03K19/00
CPC分类号： H03K19/0016 , G06F17/5022 , G06F17/5045 , H03K19/20
摘要： This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.
摘要翻译：本公开涉及集成电路（IC）中的漏电流减少。一方面，IC可以包括数字逻辑电路和极化电路。数字逻辑电路可以具有多个输入并且可以包括多个逻辑门。偏振电路可以接收备用信号和包括多个位的数字输入信号。当待机信号被去激活时，极化电路可以基于数字输入信号来控制数字逻辑电路的多个输入。然而，当待机信号被激活时，极化电路可以将数字逻辑电路的多个输入控制到与多个逻辑门相对于数字逻辑的至少一个其他状态的较小漏电流相关联的低功率状态电路。

25. 发明公开

US20240274183A1 PARALLEL ACCESS IN A MEMORY ARRAY 审中-公开
公开(公告)号：US20240274183A1
公开(公告)日：2024-08-15
申请号：US18582185
申请日：2024-02-20
申请人： Micron Technology, Inc.
发明人： Efrem Bolandrina , Andrea Martinelli , Christophe Vincent Antoine Laurent , Ferdinando Bedeschi
IPC分类号： G11C11/408 , G11C11/4074 , G11C11/4091 , G11C11/4093
CPC分类号： G11C11/4082 , G11C11/4074 , G11C11/4085 , G11C11/4091 , G11C11/4093
摘要： Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.

26. 发明公开

US20240272985A1 GENERATING A PROTECTED AND BALANCED CODEWORD 审中-公开
公开(公告)号：US20240272985A1
公开(公告)日：2024-08-15
申请号：US18582214
申请日：2024-02-20
申请人： Micron Technology, Inc.
发明人： Christophe Vincent Antoine Laurent
IPC分类号： G06F11/10
CPC分类号： G06F11/1076
摘要： Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device may receive data bits for storage. Based on the data bits, the memory device may generate a codeword that includes the data bits, parity bits, and placeholder bits. The memory device may balance the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device may store at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device may re-invert the appropriate packets to recover the original data bits.

27. 发明公开

US20240241789A1 REDUCED ERROR CODE CORRECTION POWER FOR MLC CODEWORDS 审中-公开
公开(公告)号：US20240241789A1
公开(公告)日：2024-07-18
申请号：US18404043
申请日：2024-01-04
申请人： Micron Technology, Inc.
发明人： Christophe Vincent Antoine Laurent , Riccardo Muzzetto
IPC分类号： G06F11/10 , G06F11/07
CPC分类号： G06F11/1068 , G06F11/076 , G06F11/1012
摘要： In some aspects, the techniques described herein relate to a method including: selecting a plurality of coding tables, the plurality of coding tables including an encoding table and a decoding table; building an error table using the plurality of coding tables, the error table representing potential bit errors that may occur during reading and writing to a memory device using the plurality of coding tables; masking the error table to eliminate error values in the error table meeting a preconfigured condition; determining if the error table includes one or more errors in invalid positions; and storing the error table when the error table does not include one or more errors in invalid positions.

28. 发明授权

US12039176B2 Providing multiple error correction code protection levels in memory 有权
公开(公告)号：US12039176B2
公开(公告)日：2024-07-16
申请号：US17952614
申请日：2022-09-26
申请人： Micron Technology, Inc.
发明人： Marco Sforzin , Christophe Vincent Antoine Laurent , Riccardo Muzzetto
IPC分类号： G06F3/06
CPC分类号： G06F3/0625 , G06F3/0629 , G06F3/0679
摘要： The present disclosure relates to providing multiple error correction code protection levels in memory. One device includes an array of memory cells and an operating circuit for managing operation of the array. The operating circuit comprises an encoding unit configured to generate a codeword for a first error correction code (ECC) protection level and a second ECC protection level, and decoding unit configured to perform an ECC operation on the codeword at the first ECC protection level and the second ECC protection level. The codeword comprises payload data stored in a plurality of memory cells of the array, and parity data associated with the payload data stored in parity cells of the array.

29. 发明公开

US20240053902A1 BALANCED CODEWORDS FOR REDUCING A SELECTED STATE IN MEMORY CELLS 审中-公开
公开(公告)号：US20240053902A1
公开(公告)日：2024-02-15
申请号：US17887239
申请日：2022-08-12
申请人： Micron Technology, Inc.
发明人： Christophe Vincent Antoine Laurent , Riccardo Muzzetto
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0629 , G06F3/0673
摘要： Methods, systems, and devices for balanced codewords for reducing a selected state in memory cells are described. A memory device may divide a sequence of data bits into sets of bits associated with different bit-positions in a coding scheme. The memory device may then balance a first codeword that includes the first set of the data bits in the binary domain to reach a target ratio of logic values for the codeword. Using the first codeword and the other set(s) of data bits, the memory device may balance the remaining two states in the state domain to reach an overall target distribution of the three states. The memory device may then generate one or more codeword(s) for the other set(s) of data bits so that the memory device can write all of the codewords to ternary cells.

30. 发明授权

US11733913B2 Balancing data for storage in a memory device 有权
公开(公告)号：US11733913B2
公开(公告)日：2023-08-22
申请号：US17677586
申请日：2022-02-22
申请人： Micron Technology, Inc.
发明人： Christophe Vincent Antoine Laurent , Andrea Martinelli , Marco Sforzin , Paolo Amato
IPC分类号： G06F3/06
CPC分类号： G06F3/0655 , G06F3/0602 , G06F3/0673
摘要： Methods, systems, and devices related to balancing data are described. Data may be communicated using an original set of bits that may be partitioned into segments. Each of the original set of bits may have a first value or a second value, where a weight of the original set of bits may be based on a quantity of the set of bits that have the first value. If the weight of the original set of bits is outside of a target weight range, a different, encoded set of bits may be used to represent the data, the encoded set of bits having a weight within the target weight range. The encoded set of bits may be identified based an inversion of the original set of bits in a one-at-a-time and cumulative fashion. The encoded set of bits may be stored in place of the original set of bits.

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