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21. 发明授权

US10269794B2 Semiconductor device and method of manufacture 有权
公开(公告)号：US10269794B2
公开(公告)日：2019-04-23
申请号：US15785271
申请日：2017-10-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chai-Wei Chang , Po-Chi Wu , Che-Cheng Chang
IPC分类号： H01L21/02 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/78 , H01L21/3213 , H01L21/8234
摘要： In accordance with some embodiments, conductive material is removed from over a first plurality of fins and second plurality of fins, wherein the first plurality of fins is located within a small gate length region and the second plurality of fins is located in a large gate length region. The removal is performed by initially performed a dry etch with a low pressure and a high flow rate of at least one etchant, which causes the conductive material to have a larger thickness over the second plurality of fins than over the first plurality of fins. As such, when a wet etch is utilized to remove a remainder of the conductive material, dielectric material between the second plurality of fins and the conductive material is not damaged.

22. 发明申请

US20180337246A1 Method for Fabricating Metal Gate Devices and Resulting Structures 审中-公开
公开(公告)号：US20180337246A1
公开(公告)日：2018-11-22
申请号：US16050687
申请日：2018-07-31
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Po-Chi Wu , Chai-Wei Chang , Jung-Jui Li , Ya-Lan Chang , Yi-Cheng Chao
IPC分类号： H01L29/49 , H01L29/78 , H01L21/3213 , H01L21/02 , H01L21/321 , H01L21/28
摘要： A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.

23. 发明申请

US20180047633A1 Method for Forming Semiconductor Device Structure with Gate 审中-公开
公开(公告)号：US20180047633A1
公开(公告)日：2018-02-15
申请号：US15791289
申请日：2017-10-23
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chai-Wei Chang , Po-Chi Wu , Wen-Han Fang
IPC分类号： H01L21/8234 , H01L21/28 , H01L29/66 , H01L21/311 , H01L21/3105 , H01L29/51
CPC分类号： H01L21/823437 , H01L21/28088 , H01L21/28123 , H01L21/31058 , H01L21/31144 , H01L21/823431 , H01L29/517 , H01L29/66545 , H01L29/66795
摘要： A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the gate material layer. The planarization layer includes a first material that is different from a second material of the gate material layer and a third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench.

24. 发明授权

US09543381B2 Semiconductor structure and manufacturing method of the same 有权
标题翻译：半导体结构及其制造方法相同
公开(公告)号：US09543381B2
公开(公告)日：2017-01-10
申请号：US14483636
申请日：2014-09-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Chang-Yin Chen , Tung-Wen Cheng , Che-Cheng Chang , Po-Chi Wu , Jr-Jung Lin , Chih-Han Lin
IPC分类号： H01L27/088 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/165 , H01L21/8234
CPC分类号： H01L29/0638 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L29/0649 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/7848
摘要： Present disclosure provides a semiconductor structure, including a substrate having a center portion and an edge portion, an isolation layer over the substrate; a semiconductor fin with a top surface and a sidewall surface, partially positioning in the isolation layer, a first gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at an edge portion of the substrate, and a second gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at a center portion of the substrate. A lower width of the first gate in proximity to the isolation layer is smaller than an upper width of the first gate in proximity to top surface of the semiconductor fin.
摘要翻译：本公开提供了一种半导体结构，包括具有中心部分和边缘部分的衬底，在衬底上方的隔离层; 具有顶表面和侧壁表面的半导体鳍片，部分地定位在隔离层中，覆盖半导体鳍片的顶表面的一部分和侧壁表面的一部分的第一栅极定位在衬底的边缘部分处，以及覆盖半导体鳍片的顶表面的一部分和侧壁表面的一部分的第二栅极，定位在基板的中心部分。靠近隔离层的第一栅极的较低宽度小于靠近半导体鳍片顶表面的第一栅极的上部宽度。

25. 发明授权

US09437472B2 Semiconductor line feature and manufacturing method thereof 有权
标题翻译：半导体线特征及其制造方法
公开(公告)号：US09437472B2
公开(公告)日：2016-09-06
申请号：US14192439
申请日：2014-02-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Wen-Han Fang , Po-Chi Wu
IPC分类号： H01L21/762 , H01L29/78
CPC分类号： H01L21/76232 , H01J37/321 , H01L21/3065 , H01L21/3081 , H01L21/3085 , H01L21/31116 , H01L29/78
摘要： Some embodiments of the present disclosure provide a semiconductor structure with a reduced line feature. The semiconductor structure includes a substrate, a first active region in the substrate and having a first sidewall, a second active region in the substrate and having a second sidewall, an isolation region contacting the first sidewall and the second sidewall. The above-mentioned semiconductor structure possesses a width of a top surface of the isolation region less than 50 nm and a width of a bottom surface of the isolation region more than 20 nm. Some embodiments provide a method for controlling a semiconductor line feature in a wafer, including patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a wafer, forming a trench on the wafer correlated to the line feature by performing a plasma dry etch over the wafer, and filling the trench with isolation materials.
摘要翻译：本公开的一些实施例提供具有减少的线特征的半导体结构。半导体结构包括衬底，衬底中的第一有源区，并具有第一侧壁，衬底中的第二有源区，并具有第二侧壁，接触第一侧壁和第二侧壁的隔离区。上述半导体结构具有小于50nm的隔离区的顶表面的宽度和大于20nm的隔离区的底表面的宽度。一些实施例提供了一种用于控制晶片中的半导体线特征的方法，包括对在晶片上露出具有窄于50nm的线宽的线特征的硬掩模进行图案化，在晶片上形成与线特征相关的沟槽，通过执行在晶片上进行等离子体干蚀刻，并用隔离材料填充沟槽。

26. 发明授权

US11469145B2 Method for forming semiconductor device structure with gate and resulting structures 有权
公开(公告)号：US11469145B2
公开(公告)日：2022-10-11
申请号：US16719694
申请日：2019-12-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chai-Wei Chang , Po-Chi Wu , Wen-Han Fang
IPC分类号： H01L21/8234 , H01L21/28 , H01L29/66 , H01L29/51 , H01L21/3105 , H01L21/311
摘要： A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the gate material layer. The planarization layer includes a first material that is different from a second material of the gate material layer and a third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench.

27. 发明授权

US11211380B2 Semiconductor structure and manufacturing method thereof 有权
公开(公告)号：US11211380B2
公开(公告)日：2021-12-28
申请号：US16838332
申请日：2020-04-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Che-Cheng Chang , Po-Chi Wu , Chih-Han Lin , Horng-Huei Tseng
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/66 , H01L21/84 , H01L27/12
摘要： A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are adjacent to each other and are grouped into a plurality of fin groups. The dummy semiconductor fins of the fin groups are recessed one group at a time.

28. 发明授权

US10522411B2 Method for forming semiconductor device structure with gate 有权
公开(公告)号：US10522411B2
公开(公告)日：2019-12-31
申请号：US15791289
申请日：2017-10-23
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chai-Wei Chang , Po-Chi Wu , Wen-Han Fang
IPC分类号： H01L29/66 , H01L21/8234 , H01L21/28 , H01L21/311 , H01L29/51 , H01L21/3105
摘要： A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the gate material layer. The planarization layer includes a first material that is different from a second material of the gate material layer and a third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench.

29. 发明申请

US20190252529A1 Semiconductor Device and Method 审中-公开
公开(公告)号：US20190252529A1
公开(公告)日：2019-08-15
申请号：US16390940
申请日：2019-04-22
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Bo-Feng Young , Che-Cheng Chang , Po-Chi Wu
IPC分类号： H01L29/66 , H01L29/78 , H01L29/10 , H01L21/3065
摘要： A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.

30. 发明授权

US10355110B2 FinFET and method of forming same 有权
公开(公告)号：US10355110B2
公开(公告)日：2019-07-16
申请号：US15640920
申请日：2017-07-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Che-Cheng Chang , Po-Chi Wu , Chih-Han Lin , Horng-Huei Tseng
IPC分类号： H01L29/66 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/78
摘要： A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.

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