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21. 发明授权

US09300291B2 Dynamic impedance control for input/output buffers 有权
标题翻译：输入/输出缓冲器的动态阻抗控制
公开(公告)号：US09300291B2
公开(公告)日：2016-03-29
申请号：US14499275
申请日：2014-09-29
申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
发明人： Bruce Millar
IPC分类号： H03K17/16 , H03K19/003 , H03K19/00 , G11C5/06 , G11C7/02 , G11C7/10 , G11C11/4093 , H03H7/38 , H04L25/02 , H03H17/00
CPC分类号： H03K19/0005 , G11C5/063 , G11C7/02 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C11/4093 , G11C2207/2254 , H03H7/38 , H03H17/0045 , H04L25/0278 , H04L25/028
摘要： A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.
摘要翻译：提供了执行片外驱动（OCD）和片上终端（ODT）的系统和方法。由晶体管组成的公共上拉网络和由晶体管组成的公共下拉网络被采用来实现这两个功能。在驱动模式下，上拉网络被配置为当要产生“开”输出时产生校准的驱动阻抗，并且当“关”输出为“关”时，上拉网络被配置为产生校准的驱动阻抗生成。在终端模式中，上拉网络和下拉网络被配置为分别产生校准的上拉电阻和下拉电阻，使得它们一起形成分离终端。

22. 发明授权

US09237518B2 Power saving in wireless network entities 有权
标题翻译：节能无线网络实体
公开(公告)号：US09237518B2
公开(公告)日：2016-01-12
申请号：US14551732
申请日：2014-11-24
申请人： Conversant Intellectual Property Management Incorporated
发明人： Nima Ahmadvand , Xuejun Lu , Hanwu Hu , Mouhamadou Lamine Sylla
IPC分类号： H04W52/02 , H04W36/00 , H04W84/12
CPC分类号： H04W52/0206 , H04W36/0055 , H04W52/02 , H04W52/0219 , H04W84/12 , Y02D70/00 , Y02D70/1242 , Y02D70/1262 , Y02D70/142 , Y02D70/146 , Y02D70/22
摘要： Power saving in wireless networks is disclosed. A wireless network entity that includes a module to enable a reduction in power consumption in that wireless network entity is also disclosed. The module is configured to determine that a selected wireless station of one or more wireless stations associated with the wireless network entity in a same wireless network will transmit system control information (including synchronization information and service identification information) that is normally transmitted by the wireless network entity.
摘要翻译：公开了无线网络中的省电。还公开了一种包括能够降低该无线网络实体中的功率消耗的模块的无线网络实体。该模块被配置为确定与相同无线网络中的无线网络实体相关联的一个或多个无线站的所选无线站将发送正常由无线网络发送的系统控制信息（包括同步信息和服务标识信息）实体。

23. 发明授权

US09230654B2 Method and system for accessing a flash memory device 有权
公开(公告)号：US09230654B2
公开(公告)日：2016-01-05
申请号：US13790361
申请日：2013-03-08
申请人： Jin-Ki Kim , Hong Beom Pyeon
发明人： Jin-Ki Kim , Hong Beom Pyeon
IPC分类号： G11C16/00 , G11C16/06 , G06F13/42 , G11C5/06 , G11C7/10 , G11C8/10 , G11C16/10 , G11C16/26
CPC分类号： G06F3/0611 , G06F3/0655 , G06F3/0688 , G06F13/4243 , G11C5/066 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C8/10 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2207/107 , G11C2216/30
摘要： An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

24. 发明授权

US09213389B2 Non-volatile semiconductor memory device with power-saving feature 有权
标题翻译：具有省电功能的非易失性半导体存储器件
公开(公告)号：US09213389B2
公开(公告)日：2015-12-15
申请号：US13617908
申请日：2012-09-14
申请人： HakJune Oh
发明人： HakJune Oh
IPC分类号： G06F1/26 , G06F1/32 , G06F1/12 , G11C16/16 , G11C16/32
CPC分类号： G06F1/3203 , G06F1/12 , G06F1/3275 , G11C16/16 , G11C16/32 , Y02D10/14
摘要： A non-volatile semiconductor memory device, comprising: an interface for receiving commands issued by a controller, the commands including an erase command; a functional entity with circuit components and having a terminal; a node; switchable circuitry capable of controllably switching between a first operational state in which the terminal is electrically connected to the node and a second operational state in which the terminal is electrically decoupled from the node, the node being configured to have a signal for the functional entity communicated through it when the switchable circuitry is in the first operational state; and a command processing unit configured to recognize the commands issued by the controller and, in response to recognizing the erase command, to cause the switchable circuitry to switch from the first operational state to the second operational state.
摘要翻译：一种非易失性半导体存储器件，包括：用于接收由控制器发出的命令的接口，所述命令包括擦除命令; 具有电路组件并具有终端的功能实体; 一个节点能够在端子与节点电连接的第一操作状态和端子与节点电分离的第二操作状态之间可控地切换的可切换电路，该节点被配置为具有用于功能实体通信的信号当可切换电路处于第一操作状态时; 以及命令处理单元，其被配置为识别由所述控制器发出的命令，并且响应于识别所述擦除命令，使所述可切换电路从所述第一操作状态切换到所述第二操作状态。

25. 发明授权

US09123394B2 Memory system and method using stacked memory device dice 有权
标题翻译：内存系统和方法使用堆叠式存储设备芯片
公开(公告)号：US09123394B2
公开(公告)日：2015-09-01
申请号：US14519759
申请日：2014-10-21
申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
发明人： Byoung Jin Choi
IPC分类号： G11C5/06 , G11C11/4097 , G11C11/4076 , G11C11/408 , G11C7/10 , G11C29/02
CPC分类号： H01L25/0657 , G11C5/06 , G11C7/10 , G11C7/1066 , G11C7/1093 , G11C11/401 , G11C11/4076 , G11C11/408 , G11C11/4097 , G11C29/023 , G11C29/028 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for organizing memory for a computer system including a plurality of memory devices, connected to a logic device, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device having capability to analyze and compensate for differing delays to the stacked devices stacking multiple dice divided into partitions serviced by multiple buses connected to a logic die, to increase throughput between the devices and logic device allowing large scale integration of memory with self-healing capability.
摘要翻译：一种用于组织包括连接到逻辑设备的多个存储器设备的计算机系统的存储器的方法和装置，特别是具有连接到逻辑管芯的多个堆叠存储器管芯的存储器系统，该逻辑器件具有分析能力，补偿堆叠设备的不同延迟，堆叠多个骰子被分成由连接到逻辑管芯的多个总线所服务的分区，以增加设备和逻辑设备之间的吞吐量，从而允许具有自愈能力的存储器的大规模集成。

26. 发明授权

US09098430B2 Composite semiconductor memory device with error correction 有权
标题翻译：具有误差校正的复合半导体存储器件
公开(公告)号：US09098430B2
公开(公告)日：2015-08-04
申请号：US13038461
申请日：2011-03-02
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C29/00 , G06F11/10 , G11C29/04
CPC分类号： G06F11/1044 , G06F11/1048 , G11C2029/0411 , H03M13/05 , H03M13/611
摘要： A composite semiconductor memory device, comprising: a plurality of nonvolatile memory devices; and an interface device connected to the plurality of nonvolatile memory devices and for connection to a memory controller, the interface device comprising an error correction coding (ECC) engine. Also, a memory system, comprising: a memory controller; and at least one composite semiconductor memory device configured for being written to and read from by the memory controller and comprising a built-in error correction coding (ECC) engine. Also, a memory system, comprising: a composite semiconductor memory device comprising a plurality of nonvolatile memory devices; and a memory controller connected to the at least one composite semiconductor memory device, for issuing read and write commands to the composite semiconductor memory device to cause data to be written to or read from individual ones of the nonvolatile memory devices; the composite semiconductor memory device providing error-free writing and reading of the data.
摘要翻译：一种复合半导体存储器件，包括：多个非易失性存储器件; 以及连接到所述多个非易失性存储器件并且用于连接到存储器控制器的接口设备，所述接口设备包括纠错编码（ECC）引擎。另外，一种存储器系统，包括：存储器控制器; 以及至少一个复合半导体存储器件，被配置为被存储器控制器写入和读出，并且包括内置纠错编码（ECC）引擎。另外，一种存储系统，包括：复合半导体存储器件，其包括多个非易失性存储器件; 以及存储器控制器，连接到所述至少一个复合半导体存储器件，用于向所述复合半导体存储器件发出读取和写入命令，以使数据被写入或从所述非易失性存储器件中的各个写入; 所述复合半导体存储器件提供无错误的写入和读取数据。

27. 发明申请

US20150102461A1 Cost Effective Method of Forming Embedded DRAM Capacitor 有权
标题翻译：嵌入式DRAM电容器成本有效的方法
公开(公告)号：US20150102461A1
公开(公告)日：2015-04-16
申请号：US14496797
申请日：2014-09-25
申请人： Conversant Intellectual Property Management Inc.
发明人： Soogeun Lee
IPC分类号： H01L27/108 , H01L49/02 , H01L23/532
CPC分类号： H01L27/10844 , H01L21/76844 , H01L21/76865 , H01L23/5223 , H01L23/53238 , H01L23/53295 , H01L27/108 , H01L27/10814 , H01L27/10855 , H01L27/10894 , H01L27/10897 , H01L28/75 , H01L28/87 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A high capacitance embedded metal interconnect capacitor and associated fabrication processes are disclosed for using a directional barrier metal formation sequence in a dual damascene copper process to form multi-layer stacked copper interconnect structure having reduced barrier metal layer formation at the bottom of each via hole so that the multi-layer stacked copper interconnect structure may be readily removed and replaced with high capacitance MIM capacitor layers.
摘要翻译：公开了一种高电容嵌入式金属互连电容器和相关的制造工艺，用于在双镶嵌铜工艺中使用方向性阻挡金属形成顺序，以形成在每个通孔底部形成减少的阻挡金属层的多层堆叠铜互连结构，可以容易地去除多层堆叠铜互连结构并用高电容MIM电容器层代替。

28. 发明授权

US09007834B2 Nonvolatile memory with split substrate select gates and hierarchical bitline configuration 有权
标题翻译：具有分离衬底选择门和分级位线配置的非易失性存储器
公开(公告)号：US09007834B2
公开(公告)日：2015-04-14
申请号：US13830054
申请日：2013-03-14
申请人： Mosaid Technologies Incorporated
发明人： Hyoung Seub Rhie
IPC分类号： G11C16/04 , G11C11/56 , G11C16/14
CPC分类号： G11C11/5635 , G11C16/0483 , G11C16/14
摘要： Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.
摘要翻译：通常，本公开提供了一种具有分级位线结构的非易失性存储器件，用于防止施加到存储器阵列的一组存储器单元的擦除电压泄漏到不需要擦除的其他组。本地位线耦合到每组存储器单元的存储单元。每个本地位线可以在所选择的组的读取操作期间选择性地连接到全局位线，并且当选择特定组以进行擦除时，在擦除操作期间，可以将全局位线与全局位线断开。选择用于将特定组存储器单元的每个位线电连接到全局位线的器件具有与这些存储器单元的主体电隔离的器件体。

29. 发明授权

US08964440B2 Stacked semiconductor devices including a master device 有权
标题翻译：堆叠的半导体器件包括主器件
公开(公告)号：US08964440B2
公开(公告)日：2015-02-24
申请号：US14082454
申请日：2013-11-18
申请人： Conversant Intellectual Property Management Inc.
发明人： Jin-Ki Kim
IPC分类号： G11C5/02 , G11C5/06 , G11C16/30 , H01L25/065 , H01L21/50 , H01L25/18
CPC分类号： G11C5/063 , G11C5/02 , G11C5/06 , G11C16/30 , H01L21/50 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).
摘要翻译：公开了一种包括非易失性存储器件的堆叠。堆栈中的非易失性存储器件之一是主器件，而其余存储器件或器件是从器件。

30. 发明授权

US08946897B2 Semiconductor device having metal lines with slits 有权
标题翻译：具有狭缝的金属线的半导体装置
公开(公告)号：US08946897B2
公开(公告)日：2015-02-03
申请号：US13826163
申请日：2013-03-14
申请人： Mosaid Technologies Incorporated
发明人： Sang-Hyun Yi , Young-Nam Kim
IPC分类号： H01L29/40 , H01L23/528 , H01L21/822 , H01L27/06 , H01L27/11 , H01L27/115
CPC分类号： H01L23/562 , H01L21/8221 , H01L23/528 , H01L23/585 , H01L27/0688 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1112 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit.
摘要翻译：包括半导体衬底，半导体衬底上的集成电路，覆盖集成电路的绝缘层和绝缘层上的多个金属线图案的半导体器件。多个金属线图案的第一和第二相邻的金属线图案彼此间隔一个间隔，并且第一和第二相邻金属线图案中的每一个具有至少一个狭缝。

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