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21. 发明授权

US09812334B2 Corrosion method of passivation layer of silicon wafer 有权
公开(公告)号：US09812334B2
公开(公告)日：2017-11-07
申请号：US14436037
申请日：2013-12-31
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Qiliang Sun
IPC分类号： H01L21/311 , B81C1/00
CPC分类号： H01L21/31116 , B81C1/00476 , B81C2201/0132
摘要： A corrosion method of a passivation layer (320) of a silicon wafer (300) includes: pouring hydrofluoric acid solution (100) into a container (200) with an open top; putting the silicon wafer (300) to the opening of the container (200) and one side of the silicon wafer (300) with the passivation layer (320) is opposite to the hydrofluoric acid solution (100); the hydrogen fluoride gas generated from the volatilization of the hydrofluoric acid solution (100) corrodes the passivation layer (320) of the silicon wafer (300), the corrosion time is larger or equal to (thickness of the passivation layer/corrosion rate). By means of the corrosion of the passivation layer of silicon wafer by the fluoride gas generated from the volatilization of the hydrofluoric acid solution, the fluoride gas can fully touch the passivation layer; therefore the passivation layer can be completely corroded, and the corrosion precision is high.

22. 发明授权

US09768292B2 Laterally diffused metal oxide semiconductor device and manufacturing method therefor 有权
公开(公告)号：US09768292B2
公开(公告)日：2017-09-19
申请号：US14891470
申请日：2014-05-16
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shu Zhang , Guangtao Han , Guipeng Sun
IPC分类号： H01L29/66 , H01L29/78 , H01L29/423 , H01L21/02 , H01L21/027 , H01L21/28 , H01L21/426
CPC分类号： H01L29/7816 , H01L21/02532 , H01L21/02595 , H01L21/0274 , H01L21/28035 , H01L21/426 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (S210); coating a photoresist on the surface of the wafer (S220); performing photoetching by using a first photoetching mask, and exposing a first implantation window after development (S230); performing ion implantation via the first implantation window to form a drift region in the substrate (S240); coating one layer of photoresist on the surface of the wafer again after removing the photoresist (S250); performing photoetching by using the photoetching mask of the oxide layer of the drift region (S260); and etching the oxide layer to form the oxide layer of the drift region (S270). Further provided is a laterally diffused metal oxide semiconductor device.

23. 发明申请

US20160380071A1 IGBT MANUFACTURING METHOD 有权
标题翻译： IGBT制造方法
公开(公告)号：US20160380071A1
公开(公告)日：2016-12-29
申请号：US14902516
申请日：2014-07-29
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Xiaoshe DENG , Qiang RUI , Shuo ZHANG , Genyi WANG
IPC分类号： H01L29/66 , H01L29/739 , H01L21/265 , H01L29/06 , H01L21/311
CPC分类号： H01L29/66333 , H01L21/26513 , H01L21/31111 , H01L29/0611 , H01L29/7395
摘要： An insulated gate bipolar transistor (IGBT) manufacturing method comprises the following steps: providing a semiconductor substrate of a first conducting type, the semiconductor substrate having a first major surface and a second major surface (100); forming a field-stop layer of a second conducting type on the first major surface of the semiconductor substrate (200); growing an oxide layer on the field-stop layer (300); removing the oxide layer from the field-stop layer (400); forming an epitaxial layer on the field-stop layer from which the oxide layer has been removed; and then manufacturing an IGBT on the epitaxial layer (600). Before regular manufacturing of an IGBT, the surface defects of a substrate material are eliminated as many as possible before epitaxy is formed, and the quality of an epitaxial layer is improved, thereby improving the quality of the whole IGBT.
摘要翻译：一种绝缘栅双极晶体管（IGBT）制造方法，包括以下步骤：提供第一导电类型的半导体衬底，该半导体衬底具有第一主表面和第二主表面（100）; 在半导体衬底（200）的第一主表面上形成第二导电类型的场阻止层; 在所述场 - 停止层（300）上生长氧化物层; 从所述场停止层（400）去除所述氧化物层; 在去除了氧化物层的场 - 停止层上形成外延层; 然后在外延层（600）上制造IGBT。在正常制造IGBT之前，在形成外延之前尽可能地消除基板材料的表面缺陷，提高外延层的质量，从而提高整个IGBT的质量。

24. 发明授权

US09356137B2 Power MOS device structure 有权
标题翻译：功率MOS器件结构
公开(公告)号：US09356137B2
公开(公告)日：2016-05-31
申请号：US14130483
申请日：2013-05-07
申请人： CSMC Technologies Fab1 Co., Ltd.
发明人： Shu Zhang , Yanqiang He , TseHuang Lo , HsiaoChia Wu
IPC分类号： H01L29/78 , H01L23/00 , H01L23/482
CPC分类号： H01L29/7816 , H01L23/4824 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/07 , H01L24/08 , H01L24/09 , H01L29/7835 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.
摘要翻译：公开了功率MOS器件结构的各种实施例。一方面，功率MOS器件结构包括多个LDMOS和多个接合焊盘。 LDMOS的基本单元并联并电耦合到焊盘，以耦合到LDMOS的每个基本单元的栅极端子，源极端子，漏极端子和衬底。 LDMOS的基本单元设置在焊盘下方。接合焊盘包括厚度为3.5μm至4.5μm，宽度为1.5μm至2.5μm的单层金属。本公开的功率MOS器件的焊盘下方的区域用于增加LDMOS的基本单元的数量，从而有效地降低导通电阻。

25. 发明申请

US20150214061A1 TRENCH FIELD-EFFECT DEVICE AND METHOD OF FABRICATING SAME 有权
标题翻译： TRENCH场效应装置及其制造方法
公开(公告)号：US20150214061A1
公开(公告)日：2015-07-30
申请号：US14376021
申请日：2012-07-18
申请人： Hongwei Zhou , Dongyue Gao
发明人： Hongwei Zhou , Dongyue Gao
IPC分类号： H01L21/28 , H01L29/423 , H01L29/78
CPC分类号： H01L21/28229 , H01L29/4236 , H01L29/42368 , H01L29/66734 , H01L29/7813 , H01L29/7827
摘要： The present invention provides a method of fabricating a trench field-effect device. The method includes: providing a substrate including an epitaxial layer formed on a semiconductor substrate of the substrate and a trench formed in the epitaxial layer; forming a sacrificial dielectric layer on a bottom and a sidewall of the trench; forming a heavily-doped polysilicon region at the bottom, and removing part of the sacrificial dielectric layer not covered by the heavily-doped polysilicon region to expose an epitaxial layer of the sidewall; and oxidizing the heavily-doped polysilicon region and the epitaxial layer simultaneously and forming a thick oxide layer and a trench sidewall gate dielectric layer synchronously on the bottom and the sidewall, respectively; wherein thickness of the thick oxide layer is greater than that of the trench sidewall gate dielectric layer. The method is simple, and figure of merit of the fabricated trench field-effect device is reduced.
摘要翻译：本发明提供一种制造沟槽场效应器件的方法。该方法包括：提供包括形成在衬底的半导体衬底上的外延层和形成在外延层中的沟槽的衬底; 在沟槽的底部和侧壁上形成牺牲介电层; 在底部形成重掺杂的多晶硅区域，以及去除未被重掺杂多晶硅区域覆盖的部分牺牲介电层，以露出侧壁的外延层; 并且同时氧化重掺杂多晶硅区域和外延层，并分别在底部和侧壁上同步地形成厚氧化物层和沟槽侧壁栅极电介质层; 其中厚氧化物层的厚度大于沟槽侧壁栅极电介质层的厚度。该方法简单，减小了制造的沟槽场效应器件的品质因数。

26. 发明授权

US08927386B2 Method for manufacturing deep-trench super PN junctions 有权
标题翻译：深沟超PN结的制造方法
公开(公告)号：US08927386B2
公开(公告)日：2015-01-06
申请号：US13878453
申请日：2012-05-31
申请人： Tzong Shiann Wu , Genyi Wang , Leibing Yuan , Pengpeng Wu
发明人： Tzong Shiann Wu , Genyi Wang , Leibing Yuan , Pengpeng Wu
IPC分类号： H01L21/04 , H01L21/761 , H01L29/66 , H01L29/06 , H01L21/3065
CPC分类号： H01L29/66136 , H01L21/3065 , H01L29/0619 , H01L29/0634
摘要： The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.
摘要翻译：本发明提供一种用于制造深沟槽超PN结的方法。该方法包括：沉积步骤，用于在衬底上形成外延层; 在外延层上依次形成第一电介质层和第二电介质层; 在外延层中形成深沟槽; 用外延材料完全填充深沟槽，并且外延材料超出第二介电层; 使用第三电介质填充第二电介质层的整个表面和诸如Si的外延层从具有预定高度的表面填充层填充; 在表面填充层上回蚀刻到第一介电层和外延层的界面; 以及去除第一电介质层，第二电介质层和表面填充层以平坦化Si外延材料的去除步骤。

27. 发明授权

US08895398B2 Method for manufacturing double-gate structures 有权
标题翻译：双门结构的制造方法
公开(公告)号：US08895398B2
公开(公告)日：2014-11-25
申请号：US13807307
申请日：2011-11-03
申请人： Le Wang
发明人： Le Wang
IPC分类号： H01L21/336 , H01L29/66 , H01L21/8234 , H01L21/285
CPC分类号： H01L29/66484 , H01L21/28518 , H01L21/823443 , H01L21/823468
摘要： A method is provided for manufacturing a double-gate structure. The method includes providing a substrate and forming a first gate region on a surface of the substrate using a first gate layer. The method also includes forming a second gate layer on the surface of the substrate, wherein the second gate layer covers the first gate region, forming an etch-stop layer on the second gate layer, and forming a silicide layer on the etch-stop layer. The method also includes forming a second gate region, different from the first gate region, containing the second gate layer and the silicide layer without the etch-stop layer. Further, the etch-stop layer is arranged between the second gate layer and the silicide layer to facilitate even etching of the second gate layer around the first gate region.
摘要翻译：提供了一种用于制造双栅结构的方法。该方法包括提供衬底并使用第一栅极层在衬底的表面上形成第一栅极区域。该方法还包括在衬底的表面上形成第二栅极层，其中第二栅极层覆盖第一栅极区，在第二栅极层上形成蚀刻停止层，并在蚀刻停止层上形成硅化物层。该方法还包括形成不含蚀刻停止层的不含第一栅极区的第二栅极区，其包含第二栅极层和硅化物层。此外，蚀刻停止层被布置在第二栅极层和硅化物层之间，以便于围绕第一栅极区域均匀蚀刻第二栅极层。

28. 发明授权

US08729669B2 Bipolar transistor and method for manufacturing the same 有权
标题翻译：双极晶体管及其制造方法
公开(公告)号：US08729669B2
公开(公告)日：2014-05-20
申请号：US13519252
申请日：2010-12-02
申请人： Le Wang , Linchun Gui , Kongwei Zhu , Zhiyong Zhao
发明人： Le Wang , Linchun Gui , Kongwei Zhu , Zhiyong Zhao
IPC分类号： H01L29/02
CPC分类号： H01L29/66272
摘要： A method for manufacturing a bipolar transistor includes forming a first epitaxial layer on a semiconductor substrate, forming a second epitaxial layer on the first epitaxial layer, forming an oxide layer on the second epitaxial layer, etching the oxide layer to form an opening in which the second epitaxial layer is exposed, and forming a third epitaxial layer in the opening. The first and third epitaxial layers have a first-type conductivity, and the second epitaxial layer has a second-type conductivity.
摘要翻译：一种用于制造双极晶体管的方法，包括在半导体衬底上形成第一外延层，在第一外延层上形成第二外延层，在第二外延层上形成氧化层，蚀刻氧化物层以形成开口，暴露第二外延层，并在开口中形成第三外延层。第一和第三外延层具有第一类型的导电性，第二外延层具有第二类型的导电性。

29. 发明申请

US20130196489A1 METHOD FOR MANUFACTURING DEEP-TRENCH SUPER PN JUNCTIONS 有权
标题翻译：用于制造深层超级PN结的方法
公开(公告)号：US20130196489A1
公开(公告)日：2013-08-01
申请号：US13878453
申请日：2012-05-31
申请人： Tzong Shiann Wu , Genyi Wang , Leibing Yuan , Pengpeng Wu
发明人： Tzong Shiann Wu , Genyi Wang , Leibing Yuan , Pengpeng Wu
IPC分类号： H01L29/66
CPC分类号： H01L29/66136 , H01L21/3065 , H01L29/0619 , H01L29/0634
摘要： The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.
摘要翻译：本发明提供一种用于制造深沟槽超PN结的方法。该方法包括：沉积步骤，用于在衬底上形成外延层; 在外延层上依次形成第一电介质层和第二电介质层; 在外延层中形成深沟槽; 用外延材料完全填充深沟槽，并且外延材料超出第二介电层; 使用第三电介质填充第二电介质层的整个表面和诸如Si的外延层从具有预定高度的表面填充层填充; 在表面填充层上回蚀刻到第一介电层和外延层的界面; 以及去除第一电介质层，第二电介质层和表面填充层以平坦化Si外延材料的去除步骤。

30. 发明申请

US20120178230A1 METHOD FOR FABRICATING TRENCH DMOS TRANSISTOR 审中-公开
标题翻译：用于制造TRENCH DMOS晶体管的方法
公开(公告)号：US20120178230A1
公开(公告)日：2012-07-12
申请号：US13394679
申请日：2010-09-26
申请人： Le Wang
发明人： Le Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/42372 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66719 , H01L29/66734
摘要： A method for fabricating trench DMOS transistor includes: forming an oxide layer and a barrier layer with photolithography layout sequentially on a semiconductor substrate; etching the oxide layer and the semiconductor substrate with the barrier layer as a mask to form a trench; forming a gate oxide layer on the inner wall of the trench; forming a polysilicon layer on the barrier layer, filling up the trench; etching back the polysilicon layer with the barrier layer mask to remove the polysilicon layer on the barrier layer to form a trench gate; removing the barrier layer and the oxide layer; implanting ions into the semiconductor substrate on both sides of the trench gate to form a diffusion layer; coating a photoresist layer on the diffusion layer and defining a source/drain layout thereon; implanting ions into the diffusion layer based on the source/drain layout with the photoresist layer mask to form the source/drain; forming sidewalls on both the sides of the trench gate after removing the photoresist layer; and forming a metal silicide layer on the diffusion layer and the trench gate. Effective result of the present invention is achieved with lower cost and improved efficiency of fabrication.
摘要翻译：制造沟槽DMOS晶体管的方法包括：在半导体衬底上依次形成具有光刻布局的氧化物层和阻挡层; 用阻挡层蚀刻氧化物层和半导体衬底作为掩模以形成沟槽; 在沟槽的内壁上形成栅极氧化层; 在阻挡层上形成多晶硅层，填充沟槽; 用阻挡层掩模蚀刻多晶硅层以去除阻挡层上的多晶硅层以形成沟槽栅极; 去除阻挡层和氧化物层; 在沟槽栅极的两侧将离子注入到半导体衬底中以形成扩散层; 在所述扩散层上涂覆光致抗蚀剂层并在其上限定源极/漏极布局; 基于具有光致抗蚀剂层掩模的源极/漏极布局将离子注入到扩散层中以形成源极/漏极; 在去除光致抗蚀剂层之后在沟槽栅极的两侧形成侧壁; 以及在扩散层和沟槽栅上形成金属硅化物层。本发明的有效结果是以更低的成本和更高的制造效率实现的。

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