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21. 发明授权

US11128300B1 Level shifter circuit with intermediate power domain 有权
公开(公告)号：US11128300B1
公开(公告)日：2021-09-21
申请号：US16820659
申请日：2020-03-16
申请人： Apple Inc.
发明人： Nathan F. Hanagami , Hao Zhou , Jianbao Wang , Ruopeng Wang , Ludmil N. Nikolov
IPC分类号： H03L5/00 , H03K19/0185 , H03K19/003 , H03K19/017 , H03K19/21 , H03K19/173
摘要： A level shifter circuit with an intermediate power domain and method for operating the same is disclosed. The level shifter circuit includes an input circuit, an output circuit, and an intermediate circuit. The input circuit is coupled to receive an input signal from a first voltage domain operating according to a first supply voltage, and generates a first intermediate signal. The intermediate circuit receives the first intermediate signal and generates a second intermediate signal. The output circuit receives the intermediate signal and provides an output signal into a second voltage domain operating at a second supply voltage different from the first. A voltage multiplexer is configured to provide one of the first or second supply voltages to the intermediate circuit depending on a state of the input signal.

22. 发明授权

US11101799B2 Voltage driving circuit 有权
公开(公告)号：US11101799B2
公开(公告)日：2021-08-24
申请号：US16849810
申请日：2020-04-15
申请人： SK hynix Inc.
发明人： Seung Ho Lee
IPC分类号： H02H9/04 , H03K19/003 , H03K19/17788 , H03K19/017 , H03K19/00
摘要： An input/output driving circuit may include a pad, an open-drain driving circuit, a high-voltage protection unit and a control unit. The open-drain driving circuit may be configured to output a transmission signal to the pad. The high-voltage protection unit may be configured to input a received signal from the pad. The control unit may include a gate control logic, a transmission control logic and an inverter for controlling the open-drain driving circuit. The control unit may also include a reception control logic and a well voltage generation unit for controlling the high-voltage protection unit.

23. 发明申请

US20210167095A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20210167095A1
公开(公告)日：2021-06-03
申请号：US17047740
申请日：2019-04-08
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Takahiko ISHIZU , Seiichi YONEDA
IPC分类号： H01L27/12 , H01L29/24 , H03K19/003 , H03K19/017
摘要： A semiconductor device capable of stable operation with low power consumption is provided. A logic circuit having a circuit configuration using a transistor including an oxide semiconductor in a channel formation region is included. The logic circuit is a two-input/two-output two-wire logic circuit. Transistors included in the logic circuit each include a gate and a back gate. An input terminal is electrically connected to one of a gate and a back gate of a transistor electrically connected to a wiring for supplying a high power supply potential. An output terminal is connected to the other of the gate and the back gate of the transistor electrically connected to the wiring for supplying a high power supply potential. An output terminal is electrically connected to one of a source and a drain of a transistor electrically connected to a wiring for supplying a low power supply potential. A gate or a back gate of the transistor electrically connected to the wiring for supplying a low power supply potential is electrically connected to an input terminal.

24. 发明授权

US10931281B2 Low-power active bias circuit for a high impedance input 有权
公开(公告)号：US10931281B2
公开(公告)日：2021-02-23
申请号：US16486102
申请日：2018-01-11
申请人： SPRYNGS
发明人： Nicolas Pierre Delorme , Christophe Le Blanc , Daniel Saias
IPC分类号： H03K3/011 , H03K19/017 , G01R31/3177
摘要： The invention relates to a floating state detection circuit of a node, comprising a first conductivity type MOS transistor (M1) connected between the node (N) and a first power supply line (Vss); and a second MOS transistor (M2) of conductivity type complementary to the first conductivity type, controlled by the node (N) and connected between the gate of the first transistor (M1) and a second supply line (Vdd). In addition, a third MOS transistor (M3) of the first conductivity type connected between the gate of the first transistor (M1) and the first supply line (Vss) may be controlled by the node (N).

25. 发明申请

US20200373924A1 OUTPUT DRIVING CIRCUIT 审中-公开
公开(公告)号：US20200373924A1
公开(公告)日：2020-11-26
申请号：US16989468
申请日：2020-08-10
申请人： SK hynix Inc.
发明人： Seung Ho LEE
IPC分类号： H03K19/003 , H03K19/17788 , H03K19/017 , H03K19/00
摘要： A semiconductor memory device has an output driving circuit. The output driving circuit includes a pull-down driver and a gate control logic. The pull-down driver includes first and second transistors. The first and second transistors are coupled between a pad and a ground node. The gate control logic includes third and fourth transistors. The third and fourth transistors are coupled between a pad and a first supply voltage node. The gate control logic is configured to receive a voltage of the pad and output a feedback voltage. The first transistor is controlled by the feedback voltage. The second and third transistors are controlled by the first supply voltage. The fourth transistor is controlled by the voltage of the pad.

26. 发明授权

US10833677B2 Low power logic family 有权
公开(公告)号：US10833677B2
公开(公告)日：2020-11-10
申请号：US15768549
申请日：2016-10-24
申请人： Ari Paasio
发明人： Ari Paasio
IPC分类号： H03K19/00 , H03K19/017 , H03K19/0944 , G05F3/20
摘要： According to the invention, only one type of enhancement MOS transistor type is used in implementing typical Boolean functions in hardware. Preferably, the MOS transistor type allows back bias control for adjusting and compensating the operation conditions. When implemented in PMOS only transistors, the pull-down functionality is performed by a single transistor with its gate and source connected to the output. This type of connection ensures that the pull-down functionality is performed by the leakage current of the pull-down transistor. The leakage currents of all the pull-up transistors need to be smaller than this pull-down current when all the pull-up paths are off. The ratio of these off-currents can be adjusted by the aspect ratios of the transistors. The logic type offers extremely low current consumption with low voltages and offers the possibility to avoid more complex shut-down circuitry often used in ultra low-power designs. The logic type offers higher operation speed compared to the existing solutions.

27. 发明授权

US10812082B1 Bi-directional single supply level shifter circuit 有权
公开(公告)号：US10812082B1
公开(公告)日：2020-10-20
申请号：US16586146
申请日：2019-09-27
申请人： Apple Inc.
发明人： Sujan K. Manohar , Nathan F. Hanagami
IPC分类号： H03L5/00 , H03K19/0185 , H03K17/687 , H03K19/017
摘要： A level shifter circuit included in a computer system may include bootstrap and feedback nodes. The level shifter circuit may discharge the feedback node in response to high-going transition on a received input signal generated using a first power supply signal. The level shifter circuit may also increase a voltage level of the bootstrap node in response to the high-going transition and charge the bootstrap node, in response to the discharge of the feedback node, to a voltage level of a second power supply signal that is different than a voltage level of the first power supply signal. The level shifter circuit may generate an output signal using the voltage levels of the feedback node and the second power supply signal.

28. 发明申请

US20200295723A1 Deglitching Circuit and Method in Class-D Amplifier 审中-公开
公开(公告)号：US20200295723A1
公开(公告)日：2020-09-17
申请号：US16354760
申请日：2019-03-15
申请人： STMicroelectronics (Shenzhen) R&D Co. Ltd.
发明人： Ru Feng Du , Qi Yu Liu
IPC分类号： H03G1/04 , H03K19/017 , H03F3/217 , H03K19/096 , H03K19/20 , H03K19/003 , H03G3/30
摘要： In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.

29. 发明授权

US10727833B1 High-voltage and low-voltage data paths of a hybrid output driver 有权
公开(公告)号：US10727833B1
公开(公告)日：2020-07-28
申请号：US16743872
申请日：2020-01-15
申请人： QUALCOMM Incorporated
发明人： Young Uk Yim , Jacob Schneider , Satish Krishnamoorthy , Ashwin Sethuram , Chang Ki Kwon , Mostafa Naguib Abdulla
IPC分类号： H03K19/003 , G06F3/06 , H03K19/017
摘要： A hybrid output data path is provided that supports high-voltage signaling and low-voltage signaling. The high-voltage signaling is powered by a high-power supply voltage that is greater than a low-power supply voltage that powers the low-voltage signaling.

30. 发明申请

US20200235738A1 LOW-POWER ACTIVE BIAS CIRCUIT FOR A HIGH IMPEDANCE INPUT 审中-公开
公开(公告)号：US20200235738A1
公开(公告)日：2020-07-23
申请号：US16486102
申请日：2018-01-11
申请人： SPRYNGS
发明人： Nicolas Pierre DELORME , Christophe LE BLANC , Daniel SAIAS
IPC分类号： H03K19/017 , G01R31/3177
摘要： The invention relates to a floating state detection circuit of a node, comprising a first conductivity type MOS transistor (M1) connected between the node (N) and a first power supply line (Vss); and a second MOS transistor (M2) of conductivity type complementary to the first conductivity type, controlled by the node (N) and connected between the gate of the first transistor (M1) and a second supply line (Vdd). In addition, a third MOS transistor (M3) of the first conductivity type connected between the gate of the first transistor (M1) and the first supply line (Vss) may be controlled by the node (N).

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