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31. 发明授权

US10665780B2 Selection device for use in bipolar resistive memory and manufacturing method therefor 有权
公开(公告)号：US10665780B2
公开(公告)日：2020-05-26
申请号：US16085400
申请日：2016-03-18
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Ming Liu , Qing Luo , Xiaoxin Xu , Hangbing Lv , Shibing Long , Qi Liu
IPC分类号： H01L29/51 , H01L45/00 , H01L27/24 , G11C13/00 , G11C11/56
摘要： A selector for a bipolar resistive random access memory and a method for fabricating the selector are provided. The method includes: providing a substrate; forming a lower electrode on the substrate, where the lower electrode is made of a metal, and the metal is made up of metal atoms which diffuse under an annealing condition of below 400° C.; forming a first metal oxide layer on the lower electrode; performing an annealing process on the first metal oxide layer to make the metal atoms in the lower electrode diffuse into the first metal oxide layer to form a first metal oxide layer doped with metal atoms; forming a second metal oxide layer on the first metal oxide layer doped with metal atoms; forming an upper electrode layer on the second metal oxide layer; and patterning the upper electrode layer to form an upper electrode.

32. 发明授权

US10573658B2 Method of manufacturing three-dimensional vertical and semiconductor device 有权
公开(公告)号：US10573658B2
公开(公告)日：2020-02-25
申请号：US15311000
申请日：2014-07-10
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Zongliang Huo
IPC分类号： H01L27/11582 , H01L21/324 , H01L21/28
摘要： A method of manufacturing three-dimensional semiconductor device includes the steps of: forming a stack structure of a plurality of a first material layers and a second material layers on a substrate in the memory cell region; etching the stack structure to form a plurality of trenches; forming channel layers in the plurality of trenches; and reducing the surface roughness and the interface state by performing annealing treatment to at least one surface of the channel layers.

33. 发明授权

US10475935B2 Nanometer semiconductor devices having high-quality epitaxial layer 有权
公开(公告)号：US10475935B2
公开(公告)日：2019-11-12
申请号：US15371431
申请日：2016-12-07
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huilong Zhu
IPC分类号： H01L29/786 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/775 , B82Y10/00 , H01L29/10
摘要： There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.

34. 发明授权

US10475807B2 Three-dimensional memory device and manufacturing method thereof 有权
公开(公告)号：US10475807B2
公开(公告)日：2019-11-12
申请号：US15503833
申请日：2014-09-25
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Zongliang Huo , Ming Liu , Lei Jin
IPC分类号： H01L27/11578 , H01L27/11582 , H01L49/02
摘要： A method for manufacturing three-dimensional memory, comprising the steps of: forming a stack structure composed of a plurality of first material layers and a plurality of second material layers on a substrate; etching the stack structure to expose the substrate, forming a plurality of first vertical openings; forming a filling layer in each of the first openings; etching the stack structure around each of the first openings to expose the substrate, forming a plurality of second vertical openings; forming a vertical channel layer and a drain in each of the second openings; removing the filling layer by selective etching, re-exposing the first openings; partially or completely removing the second material layers by lateral etching, leaving a plurality of recesses; forming a plurality of gate stack structure in the recesses; forming a plurality of common sources on and/or in the substrate at the bottom of each of the first openings. In accordance with the three-dimensional memory manufacturing method of the present invention, the deep trenches of word-line in the TCAT three-dimensional device are replaced with deep-hole etching to realize the same function, thereby improving the integration density, simplifying the etching process of stacked structure, and maintaining the control performance of the metal gate.

35. 发明申请

US20190235858A1 APPARATUS AND METHOD FOR CONFIGURING OR UPDATING PROGRAMMABLE LOGIC DEVICE 审中-公开
公开(公告)号：US20190235858A1
公开(公告)日：2019-08-01
申请号：US16337978
申请日：2017-04-21
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Yuanlu XIE , Kun ZHANG , Haitao SUN , Jing LIU , Jinshun BI , Ming LIU
IPC分类号： G06F8/654 , G06F13/42 , G06F1/3296
CPC分类号： G06F8/654 , G06F1/3296 , G06F8/71 , G06F13/4282
摘要： An apparatus and a method for configuring or updating a programmable logic device are provided. The apparatus includes a control module and a storage module connected to the control module. The control module includes: a JTAG interface for connecting the control module to a JTAG host, and a configuration interface compatible with a to-be-configured programmable logic device. The control module is configured to: after receiving a first control instruction including configuration information via the JTAG interface, store the configuration information into the storage module; and after receiving a configuration instruction, read the configuration information to configure the to-be-configured programmable logic device. A configuration clock used in a process that the control module configures the to-be-configured programmable logic device is generated from the to-be-configured programmable logic device, the control module or an external clock source.

36. 发明授权

US10157956B2 Method of monolithic integration of hyperspectral image sensor 有权
公开(公告)号：US10157956B2
公开(公告)日：2018-12-18
申请号：US15477191
申请日：2017-04-03
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Hushan Cui , Jinjuan Xiang , Xiaobin He , Tao Yang , Junfeng Li , Chao Zhao
IPC分类号： H01L21/00 , H01L27/146 , H01L31/0216 , H01L31/0232
摘要： A method for monolithic integration of a hyperspectral image sensor is provided, which includes: forming a bottom reflecting layer on a surface of the photosensitive region of a CMOS image sensor wafer; forming a transparent cavity layer composed of N step structures on the bottom reflecting layer through area selective atomic layer deposition processes, where N=2m, m≥1 and m is a positive integer; and forming a top reflecting layer on the transparent cavity layer. With the method, non-uniformity accumulation due to etching processes in conventional technology is minimized, and the cavity layer can be made of materials which cannot be etched. Mosaic cavity layers having such repeated structures with different heights can be formed by extending one-dimensional ASALD, such as extending in another dimension and forming repeated regions, which can be applied to snapshot hyperspectral image sensors, for example, pixels, and greatly improving performance thereof.

37. 发明授权

US10128375B2 Strained FinFET and method for manufacturing the same 有权
公开(公告)号：US10128375B2
公开(公告)日：2018-11-13
申请号：US14419833
申请日：2012-08-24
申请人： Huilong Zhu , Miao Xu
发明人： Huilong Zhu , Miao Xu
IPC分类号： H01L21/00 , H01L29/78 , H01L29/10 , H01L21/3065 , H01L21/308 , H01L29/06 , H01L29/161 , H01L29/66 , H01L29/165
摘要： An FinFET and a method for manufacturing the same are disclosed. The FinFET comprises: a semiconductor substrate; a stress layer on the semiconductor substrate; a semiconductor fin on the stress layer, the semiconductor fin having two sidewalls extending in its length direction; a gate dielectric on the sidewalls of the semiconductor fin; a gate conductor on the gate dielectric; and a source region and a drain region at two ends of the semiconductor fin, wherein the stress layer extends below and in parallel with the semiconductor fin, and applies stress to the semiconductor fin in the length direction of the semiconductor fin.

38. 发明授权

US09934975B2 N-type MOSFET and method for manufacturing the same 有权
公开(公告)号：US09934975B2
公开(公告)日：2018-04-03
申请号：US14494447
申请日：2014-09-23
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu , Qiuxia Xu , Yanbo Zhang , Hong Yang
IPC分类号： H01L21/28 , H01L29/66 , H01L29/49 , H01L29/51
CPC分类号： H01L21/28105 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/66537 , H01L29/66545
摘要： An N-type MOSFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming source/drain regions in a semiconductor substrate. The method also includes forming an interfacial oxide layer on the semiconductor substrate. The method also includes forming a high-k gate dielectric layer on the interfacial oxide layer. The method also includes forming a first metal gate layer on the high-k gate dielectric layer. The method also includes implanting dopants into the first metal gate layer through conformal doping. The method also includes annealing a gate stack to change an effective work function of the gate stack which includes the first metal gate layer, the high-k gate dielectric, and the interfacial oxide layer.

39. 发明授权

US09911617B2 Etching method 有权
公开(公告)号：US09911617B2
公开(公告)日：2018-03-06
申请号：US15299169
申请日：2016-10-20
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Junjie Li , Junfeng Li , Qinghua Yang , Jinbiao Liu , Xiaobin He
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00 , H01L21/3065 , H01L21/308 , H01L21/3213
CPC分类号： H01L21/3065 , H01L21/3085 , H01L21/32136 , H01L21/32139
摘要： The invention discloses a novel dry etching method, which comprises the following steps: forming a to-be-etched layer on a semiconductor substrate; forming a masking material on the to-be-etched layer; carrying out dry etching on the masking material and the to-be-etched layer; simultaneously carrying out lateral etching (parallel to the surface of the substrate) of a masking layer and longitudinal etching (vertical to the surface of the substrate) of the to-be-etched layer; and obtaining the inclination angle (the included angle between a slope surface and the surface of the substrate) of the corresponding etched slope surface by accurately controlling the speed ratio. The method can flexibly adjust the inclination angle of the etched slope surface within a large range (0-90 degrees), and especially has advantages in the field of the application with a small inclination angle (smaller than 20 degrees) of the etched slope surface in comparison with a conventional etching method.

40. 发明授权

US09780200B2 Semiconductor arrangement for a FinFET and method for manufacturing the same 有权
公开(公告)号：US09780200B2
公开(公告)日：2017-10-03
申请号：US14411073
申请日：2014-01-16
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu
IPC分类号： H01L29/66 , H01L21/62 , H01L29/78 , H01L21/762
CPC分类号： H01L29/6681 , H01L21/26506 , H01L21/762 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L21/823821 , H01L21/823878 , H01L27/0886 , H01L27/0924 , H01L29/0649 , H01L29/6653 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A semiconductor arrangement and a method for manufacturing the same. An arrangement may include a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate. The first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack. The second FinFET includes a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; an isolation section self-aligned to a space defined by the dummy gate spacer. The isolation section electrically isolates the first FinFET from the second FinFET; and an insulation layer disposed under and abutting the isolation section.

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