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31. 发明申请

US20150082072A1 MEMORY CONTROLLER WITH FLEXIBLE DATA ALIGNMENT TO CLOCK 审中-公开
公开(公告)号：US20150082072A1
公开(公告)日：2015-03-19
申请号：US14486484
申请日：2014-09-15
申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
发明人： Hong Beom PYEON
IPC分类号： G06F1/10
CPC分类号： G06F1/10 , G11C5/025 , G11C7/02 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C7/20 , G11C7/22 , G11C7/222 , H01L25/0657 , H01L2224/32145 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H04L7/0008 , H01L2924/00 , H01L2924/00012
摘要： A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller.

32. 发明申请

US20150081155A1 Method and Apparatus for Starting an Engine in a Hybrid Vehicle 审中-公开
标题翻译：用于在混合动力车辆中起动发动机的方法和装置
公开(公告)号：US20150081155A1
公开(公告)日：2015-03-19
申请号：US14553244
申请日：2014-11-25
申请人： Conversant Intellectual Property Management Inc.
发明人： Nicolas Louis Bouchon
IPC分类号： B60K6/46 , B60W30/192 , B60W10/06 , B60W10/08 , B60K6/547 , B60W10/115
CPC分类号： B60W20/30 , B60K6/46 , B60K6/48 , B60K6/543 , B60K6/547 , B60L15/2054 , B60L50/16 , B60L50/40 , B60L58/12 , B60L58/21 , B60L2200/12 , B60L2210/40 , B60L2220/12 , B60L2220/16 , B60L2240/12 , B60L2240/421 , B60L2240/423 , B60L2240/441 , B60L2240/443 , B60L2240/486 , B60L2240/507 , B60L2240/80 , B60L2260/26 , B60L2270/145 , B60W10/02 , B60W10/06 , B60W10/08 , B60W10/10 , B60W10/101 , B60W10/11 , B60W10/115 , B60W20/00 , B60W20/10 , B60W30/192 , B60W2510/0695 , B60W2510/081 , B60W2510/244 , B60W2520/10 , B60W2710/021 , B60W2710/025 , B60W2710/081 , B60W2710/1005 , B60W2720/10 , B60Y2200/92 , B60Y2300/192 , B60Y2300/42 , B60Y2300/43 , B60Y2300/50 , B60Y2300/60 , B60Y2400/70 , B60Y2400/72 , Y02T10/6221 , Y02T10/6286 , Y02T10/645 , Y02T10/70 , Y02T10/7005 , Y02T10/7022 , Y02T10/7044 , Y02T10/7061 , Y02T10/7077 , Y02T10/7241 , Y02T10/7275 , Y10S903/918 , Y10S903/919 , Y10S903/93 , Y10T477/23 , Y10T477/641 , Y10T477/656
摘要： A method and apparatus for starting an engine in a hybrid vehicle being driven by an electric motor is disclosed. The motor is operably configured to deliver mechanical power through an automatic transmission to at least one vehicle drive wheel to cause an acceleration of the vehicle. The method involves coupling the engine to the motor to cause an inertial load on the motor thus causing the motor to decelerate to a reduced rotational speed to provide a starting torque to the engine for starting the engine, and causing the automatic transmission to change gear ratio to a target gear ratio associated with the reduced rotational speed while causing the motor to decelerate, the motor being operable to deliver increased torque at the reduced rotational speed, thereby generally maintaining the acceleration of the vehicle.
摘要翻译：公开了一种用于启动由电动机驱动的混合动力车辆中的发动机的方法和装置。马达被可操作地构造成通过自动变速器将机械动力输送到至少一个车辆驱动轮以引起车辆的加速。该方法包括将发动机耦合到电动机以在电动机上引起惯性负载，从而使电动机减速到降低的转速，以向起动发动机的发动机提供起动转矩，并使自动变速器改变变速比达到在使电机减速的同时降低转速的目标传动比，电动机可操作以在降低的转速下传递增加的扭矩，从而通常保持车辆的加速度。

33. 发明授权

US08964440B2 Stacked semiconductor devices including a master device 有权
标题翻译：堆叠的半导体器件包括主器件
公开(公告)号：US08964440B2
公开(公告)日：2015-02-24
申请号：US14082454
申请日：2013-11-18
申请人： Conversant Intellectual Property Management Inc.
发明人： Jin-Ki Kim
IPC分类号： G11C5/02 , G11C5/06 , G11C16/30 , H01L25/065 , H01L21/50 , H01L25/18
CPC分类号： G11C5/063 , G11C5/02 , G11C5/06 , G11C16/30 , H01L21/50 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).
摘要翻译：公开了一种包括非易失性存储器件的堆叠。堆栈中的非易失性存储器件之一是主器件，而其余存储器件或器件是从器件。

34. 发明申请

US20150049543A1 PHASE CHANGE MEMORY WORD LINE DRIVER 审中-公开
标题翻译：相变存储器字线驱动器
公开(公告)号：US20150049543A1
公开(公告)日：2015-02-19
申请号：US14530798
申请日：2014-11-02
申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
发明人： Hong Beom PYEON
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C8/08 , G11C8/14 , G11C13/0004 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C2013/0071
摘要： A method for improving sub-word line response comprises generating a variable substrate bias determined by at least one user parameter. The variable substrate bias is applied to a sub-word line driver in a selected sub-block of a memory. A voltage disturbance on a sub-word line in communication with the sub-word line driver is minimized by modifying a variable substrate bias of the sub-word line driver to change a transconductance of the sub-word line driver thereby.
摘要翻译：一种用于改善子字线响应的方法包括生成由至少一个用户参数确定的可变衬底偏置。可变衬底偏置被施加到存储器的所选子块中的子字线驱动器。通过修改子字线驱动器的可变衬底偏置来改变子字线驱动器的跨导，从而最小化与子字线驱动器通信的子字线上的电压干扰。

35. 发明申请

US20150021773A1 Through Semiconductor via Structure with Reduced Stress Proximity Effect 审中-公开
标题翻译：通过半导体通过结构减少应力接近效应
公开(公告)号：US20150021773A1
公开(公告)日：2015-01-22
申请号：US14312052
申请日：2014-06-23
申请人： Conversant Intellectual Property Management Inc.
发明人： Soogeun Lee
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76816 , H01L21/76843 , H01L21/76898 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device and associated fabrication process are disclosed for forming a through semiconductor via (TSV) conductor structure in a semiconductor substrate with active circuitry formed on a first substrate surface where the TSV conductor structure includes multiple small diameter conductive vias extending through the first substrate surface and into the semiconductor substrate by a predetermined depth and a large diameter conductive via formed to extend from the multiple small diameter conductive vias and through a second substrate surface opposite to the first substrate surface.
摘要翻译：公开了一种用于在半导体衬底中形成贯穿半导体通孔（TSV）导体结构的集成电路器件和相关的制造工艺，其中有源电路形成在第一衬底表面上，其中TSV导体结构包括延伸穿过第一衬底的多个小直径导电通孔表面并通过形成为从多个小直径导电通孔延伸并通过与第一衬底表面相对的第二衬底表面的预定深度和大直径导电通孔进入半导体衬底。

36. 发明申请

US20150009761A1 CLOCK MODE DETERMINATION IN A MEMORY SYSTEM 审中-公开
公开(公告)号：US20150009761A1
公开(公告)日：2015-01-08
申请号：US14491440
申请日：2014-09-19
申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
发明人： Peter B. GILLINGHAM , Graham ALLAN
IPC分类号： G11C16/10
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

37. 发明申请

US20140375354A1 Low Leakage and Data Retention Circuitry 审中-公开
标题翻译：低泄漏和数据保留电路
公开(公告)号：US20140375354A1
公开(公告)日：2014-12-25
申请号：US14480143
申请日：2014-09-08
申请人： Conversant Intellectual Property Management Inc.
发明人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
IPC分类号： H03K19/003 , H03K19/00 , H03K17/10 , H03K3/356 , H03K5/14
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/144 , G11C5/148 , H02M3/07 , H03K3/0372 , H03K3/356086 , H03K3/356113 , H03K5/14 , H03K17/102 , H03K19/00315
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
摘要翻译：集成电路包括第一电路和睡眠晶体管电路。第一个电路接收输入信号并处理输入信号。第一电路还保持具有低泄漏的睡眠状态的数据。睡眠晶体管电路耦合到第一电路并且接收具有负电压的睡眠信号。休眠电路降低处于休眠状态的第一电路的功耗，以便在将数据保留在第一电路中的同时基于睡眠信号具有低泄漏。

38. 发明申请

US20140325178A1 SYSTEM HAVING ONE OR MORE MEMORY DEVICES 审中-公开
标题翻译：具有一个或多个记忆设备的系统
公开(公告)号：US20140325178A1
公开(公告)日：2014-10-30
申请号：US14331036
申请日：2014-07-14
申请人： Conversant Intellectual Property Management Inc.
发明人： Steven PRZYBYLSKI , Roland SCHUETZ , HakJune OH , Hong Beom PYEON
IPC分类号： G06F3/06
CPC分类号： G06F3/0629 , G06F3/0604 , G06F3/0673 , G06F13/4243 , G06F13/4256 , G11C7/10 , G11C7/1042 , G11C7/20 , G11C8/06 , G11C8/10 , Y02D10/14 , Y02D10/151
摘要： A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.
摘要翻译：一种在环形拓扑组织中具有串联连接的存储器件以实现高速性能的系统。存储器件具有动态可配置的数据宽度，使得系统可以以高达最大公共数量的有源数据焊盘操作以最大化性能，或者使用单个有源数据焊盘操作以最小化功耗。因此，系统可以包括具有不同数据宽度的存储器件的混合。通过在广播操作中通过从存储器控制器的所有存储器装置串行传播的单个命令的发布来动态地配置存储器件。通过实施数据输出禁止算法来确保系统的稳健运行，当从其正确的序列中接收到读取输出控制信号时，该算法防止有效数据被提供给存储器控制器。

39. 发明申请

US20140313831A1 DEVICE SELECTION SCHEMES IN MULTI CHIP PACKAGE NAND FLASH MEMORY SYSTEM 有权
标题翻译：多芯片封装NAND闪存存储器系统中的器件选择方案
公开(公告)号：US20140313831A1
公开(公告)日：2014-10-23
申请号：US14321987
申请日：2014-07-02
申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
发明人： Jin-Ki KIM
IPC分类号： G11C16/06
CPC分类号： G11C15/046 , G11C7/109 , G11C8/12 , G11C16/0483 , G11C16/06 , G11C16/08
摘要： Device selection schemes in multi-chip package NAND flash memory systems are provided. A memory system is provided that has a memory controller, and a number of memory devices connected to the controller via a common bus with a multi-drop connection. The memory controller performs device selection by command. A corresponding memory controller is provided which performs device selection by command. Alternatively, device selection is performed by address. A memory device is provided use in memory system comprising a memory controller, and a number of memory devices inclusive of the memory device connected to the controller via a common bus with a multi-drop connection. The memory device has a register containing a device identifier, and a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match. The memory device is selected if the device identifier comparator determines there is a match.
摘要翻译：提供了多芯片封装NAND闪速存储器系统中的器件选择方案。提供了一种存储器系统，其具有存储器控制器以及通过具有多点连接的公共总线连接到控制器的多个存储器件。内存控制器通过命令执行设备选择。提供相应的存储器控制器，其通过命令执行设备选择。或者，设备选择由地址执行。在存储器系统中提供存储器装置，该存储器系统包括存储器控制器，以及包括通过具有多点连接的公共总线连接到控制器的存储器件的多个存储器件。存储器件具有包含器件标识符的寄存器和将接收到的输入地址的选定位与寄存器的内容进行比较的器件标识符比较器，以确定是否存在匹配。如果设备标识符比较器确定存在匹配，则选择存储器件。

40. 发明授权

US08855121B2 Congestion management in a network 有权
标题翻译：网络中的拥塞管理
公开(公告)号：US08855121B2
公开(公告)日：2014-10-07
申请号：US13795070
申请日：2013-03-12
申请人： Conversant Intellectual Property Management Inc.
发明人： David Brown
IPC分类号： H04L12/28 , H04L12/741
CPC分类号： H04L45/54 , G06F17/30949 , H04L47/21 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： Management of congestion level, in a computer-related context, is disclosed. Also disclosed is a system generating a plurality of computer network-related tables during system operation. A number of the tables are each separately indexed by a different index. The system includes at least one tangible computer-readable medium adapted to store, at each indexed location, a swap count providing an indication of the congestion level of the indexed location. The system also includes insert logic stored as instructions on the at least one medium for execution. When executed, the insert logic is operable to: i) insert, when a predetermined condition has been satisfied, a new entry by overwriting the current entry stored in the indexed location having the lowest swap count; and ii) update the swap counts in each of the indexed locations in a manner that maintains the total swap count at least substantially constant over time.
摘要翻译：在计算机相关的背景下披露拥塞程度的管理。还公开了在系统操作期间生成多个计算机网络相关表的系统。多个表分别由不同的索引分别索引。该系统包括至少一个有形的计算机可读介质，其适于在每个索引的位置处存储提供索引位置的拥塞级别的指示的交换计数。该系统还包括存储为用于执行的至少一个介质上的指令的插入逻辑。当执行时，插入逻辑可操作为：i）当已经满足预定条件时，通过重写存储在具有最低交换次数的索引位置中的当前条目来插入新条目; 以及ii）以保持总交换计数至少基本上恒定的方式来更新每个索引位置中的交换计数。

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