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31. 发明申请

US20140189239A1 PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES 审中-公开
标题翻译：具有虚拟聚合的CORES和CACHE SLICES的处理程序
公开(公告)号：US20140189239A1
公开(公告)日：2014-07-03
申请号：US13729579
申请日：2012-12-28
申请人： Herbert H. Hum , Brinda Ganesh , James R. Vash , Ganesh Kumar , Leena K. Puthiyedath , Scott J. Erlanger , Eric J. Dehaemer , Adrian C. Moga , Michelle M. Sebot , Richard L. Carlson , David Bubien , Eric Delano
发明人： Herbert H. Hum , Brinda Ganesh , James R. Vash , Ganesh Kumar , Leena K. Puthiyedath , Scott J. Erlanger , Eric J. Dehaemer , Adrian C. Moga , Michelle M. Sebot , Richard L. Carlson , David Bubien , Eric Delano
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/084
摘要： A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
摘要翻译：一方面的处理器包括多个逻辑处理器，每个逻辑处理器具有一个或多个相应的较低级别的高速缓存。共享的较高级缓存由多个逻辑处理器共享。共享的较高级缓存包括用于每个逻辑处理器的分布式缓存片。处理器包括用于将对应逻辑处理器的一个或多个较低级别高速缓存中的访问指向与对应于逻辑处理器的虚拟集群中的分布式高速缓存片段的子集的逻辑。还公开了其他处理器，方法和系统。

32. 发明授权

US08327228B2 Home agent data and memory management 失效
标题翻译：家庭代理数据和内存管理
公开(公告)号：US08327228B2
公开(公告)日：2012-12-04
申请号：US12571381
申请日：2009-09-30
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G11C29/00
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.
摘要翻译：描述与归属代理数据和存储器管理有关的方法和装置。在一个实施例中，洗涤器逻辑通过将校正的数据版本写回到目标位置来校正与目标地址相对应的存储器中的位置处的错误。在一个实施例中，映射逻辑响应于对应于目录高速缓存的多个错误超过阈值来映射目录高速缓存的索引或方式。还公开了其他实施例。

33. 发明授权

US08327113B2 Method, system, and apparatus for dynamic reconfiguration of resources 有权
公开(公告)号：US08327113B2
公开(公告)日：2012-12-04
申请号：US12235968
申请日：2008-09-23
申请人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose A. Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose A. Vargas
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

34. 发明申请

US20110078384A1 MEMORY MIRRORING AND MIGRATION AT HOME AGENT 有权
标题翻译：在家庭代理记忆转移和移动
公开(公告)号：US20110078384A1
公开(公告)日：2011-03-31
申请号：US12571382
申请日：2009-09-30
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G06F12/08 , G06F12/00 , G06F12/16
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.
摘要翻译：描述了与归属代理（HA）的内存镜像和迁移有关的方法和设备。在一个实施例中，归属代理可以在从属代理处镜像其数据。在一些实施例中，目录中的位可以指示高速缓存行的状态。还公开了其他实施例。

35. 发明申请

US20100332767A1 Controllably Exiting An Unknown State Of A Cache Coherency Directory 有权
标题翻译：可控地退出高速缓存一致性目录的未知状态
公开(公告)号：US20100332767A1
公开(公告)日：2010-12-30
申请号：US12492280
申请日：2009-06-26
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0817 , G06F9/5033 , G06F2212/1032
摘要： In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，一种方法包括从第一高速缓存代理接收读取请求，并且如果与请求相关联的目录条目处于未知状态，则向至少一个其他高速缓存代理发送无效侦听消息以使高速缓存中的信息无效与读取请求的位置相对应的其他高速缓存代理的位置，以使目录项进入已知状态。描述和要求保护其他实施例。

36. 发明申请

US20090024715A1 Method, System, and Apparatus for Dynamic Reconfiguration of Resources 有权
公开(公告)号：US20090024715A1
公开(公告)日：2009-01-22
申请号：US12235968
申请日：2008-09-23
申请人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhiles Kumar , Jay Jayasimha , Jose A. Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhiles Kumar , Jay Jayasimha , Jose A. Vargas
IPC分类号： G06F15/167
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

37. 发明授权

US07398374B2 Multi-cluster processor for processing instructions of one or more instruction threads 失效
标题翻译：用于处理一个或多个指令线程的指令的多集群处理器
公开(公告)号：US07398374B2
公开(公告)日：2008-07-08
申请号：US10083872
申请日：2002-02-27
申请人： Eric DeLano
发明人： Eric DeLano
IPC分类号： G06F9/30
CPC分类号： G06F9/3891 , G06F9/3828 , G06F9/3851 , G06F9/3885
摘要： The invention provides a processor that processes bundles of instructions preferentially through clusters or execution units according to thread characteristics. The cluster architectures of the invention preferably include capability to process “multi-threaded” instructions. Selectively, the architecture either (a) processes singly-threaded instructions through a single cluster to avoid bypassing and to increase throughput, or (b) processes singly-threaded instructions through multiple processes to increase “per thread” performance. The architecture may be “configurable” to operate in one of two modes: in a “wide” mode of operation, the processor's internal clusters collectively process bundled instructions of one thread of a program at the same time; in a “throughput” mode of operation, those clusters independently process instruction bundles of separate program threads. Clusters are often implemented on a common die, with a core and register file per cluster.
摘要翻译：本发明提供了一种根据线程特征优先地通过簇或执行单元处理指令束的处理器。本发明的集群架构优选地包括处理“多线程”指令的能力。选择性地，架构（a）通过单个集群处理单线程指令，以避免绕过并增加吞吐量，或（b）通过多个进程处理单线程指令以增加“每线程”性能。架构可以是“可配置的”以在两种模式之一中操作：在“宽”操作模式中，处理器的内部集群同时处理程序的一个线程的捆绑指令; 在“吞吐量”操作模式下，这些集群独立地处理单独的程序线程的指令包。群集通常在一个公用的模具上实现，每个群集具有核心和注册文件。

38. 发明授权

US06941489B2 Checkpointing of register file 有权
标题翻译：注册文件的检查点
公开(公告)号：US06941489B2
公开(公告)日：2005-09-06
申请号：US10084533
申请日：2002-02-27
申请人： Eric DeLano
发明人： Eric DeLano
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/1405
摘要： The invention performs an extra read from a register of a register file prior to writing to that register. The data from the extra read is stored in a buffer (e.g., another register file). After a “checkpoint” period, a check is made as to whether any data errors have occurred; if there are no errors, the buffer is flushed and processing continues per normal; if there are errors, the register file is rewritten with contents from the buffer and the program counter is reset to the prior checkpoint, wherein after processing re-executes program instructions from the last checkpoint. The checkpointing period may be defined by the memory size of the buffer; typically that buffer has a fraction of the memory capacity of the register file, since a flush occurs at every checkpoint. The register file of the invention may utilize an extra read port with the register file to perform the extra read. The extra read may occur for every write to the register file; alternatively, the extra read may occur for a subset of the writes to the register file.
摘要翻译：本发明在写入该寄存器之前从寄存器堆的寄存器执行额外的读取。来自额外读取的数据被存储在缓冲器（例如，另一个寄存器文件）中。在“检查点”期之后，检查是否发生了任何数据错误; 如果没有错误，缓冲区被刷新，并且处理继续正常; 如果存在错误，则使用来自缓冲器的内容重写寄存器文件，并且将程序计数器重置为先前的检查点，其中在处理之后从最后检查点重新执行程序指令。检查点周期可以由缓冲器的存储器大小来定义; 通常，缓冲区具有寄存器文件的存储容量的一小部分，因为在每个检查点都发生冲突。本发明的寄存器文件可以利用额外的读取端口与寄存器文件来执行额外的读取。对寄存器文件的每次写入可能会发生额外读取; 或者，对寄存器文件的写入的子集可能发生额外的读取。

39. 发明授权

US5603004A Method for decreasing time penalty resulting from a cache miss in a multi-level cache system 失效
标题翻译：用于减少由多级缓存系统中的高速缓存未命中引起的时间损失的方法
公开(公告)号：US5603004A
公开(公告)日：1997-02-11
申请号：US196042
申请日：1994-02-14
申请人： Gordon Kurpanek , Eric Delano , Michael A. Buckley , William R. Bryg
发明人： Gordon Kurpanek , Eric Delano , Michael A. Buckley , William R. Bryg
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/0897 , G06F12/0864 , G06F12/12 , G06F12/0862
摘要： A cache system buffers data stored in a main memory and utilized by a processor. The cache system includes a first cache, a second cache, a first transfer channel, a second transfer channel and a third transfer channel. The first cache is fully associative. The second cache is directly mapped. The first transfer channel transfers data lines from the main memory to the first cache. The second transfer channel transfers data lines from the first cache to the second cache. The third transfer channel transfers data lines from the second cache to the main memory. Accesses of data lines from the first cache and the second cache are performed in parallel.
摘要翻译：缓存系统缓冲存储在主存储器中并由处理器使用的数据。高速缓存系统包括第一高速缓存，第二高速缓存，第一传送通道，第二传送通道和第三传送通道。第一个缓存是完全关联的。第二个缓存直接映射。第一个传输通道将数据线从主存储器传输到第一个缓存。第二传输信道将数据线从第一高速缓存传送到第二高速缓存。第三传送通道将数据线从第二高速缓存传送到主存储器。并行执行来自第一高速缓存和第二高速缓存的数据线的访问。

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