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31. 发明授权

US07203816B2 Multi-processor system apparatus allowing a compiler to conduct a static scheduling process over a large scale system of processors and memory modules 有权
标题翻译：多处理器系统设备允许编译器在大规模处理器和存储器模块系统上进行静态调度过程
公开(公告)号：US07203816B2
公开(公告)日：2007-04-10
申请号：US10085132
申请日：2002-03-01
申请人： Tomohiro Morimura , Hideharu Amano
发明人： Tomohiro Morimura , Hideharu Amano
IPC分类号： G06F15/00 , G06F15/16
CPC分类号： G06F15/17393
摘要： A multi-processor system apparatus allows a compiler to perform a static scheduling action easily and can conduct the transfer of data packets without collision in response to a common pattern of simultaneous access demands. Processor elements are interconnected by a multi-stage interconnection network having multiple stages. As each of switching elements in the multi-stage interconnection network is preliminarily subjected to the static scheduling action of a compiler. The multi-stage interconnection network is emulated without producing collision of data. When the transfer of packets is carried out in one clos network arrangement of the multi-stage interconnection network, the scheduling of switching elements SE0 to SE3 in the exchanger at Level 1 is determined so that a packet lost in the arbitration is transferred through the free port of any applicable one of the switching elements.
摘要翻译：多处理器系统装置允许编译器容易地执行静态调度操作，并且可以响应于同时访问需求的共同模式而进行数据包的传输而不发生冲突。处理器元件通过具有多个级的多级互连网络互连。由于多级互联网络中的各开关元件预先受到编译器的静态调度动作的影响。模拟多级互连网络而不产生数据冲突。当在多级互连网络的一个闭合网络布置中进行分组的传送时，确定在层1的交换机中的交换单元SE 0至SE 3的调度，使得仲裁中丢失的分组通过任何适用的一个开关元件的自由端口。

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