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31. 发明申请

US20050091625A1 Process and apparatus for placement of cells in an IC during floorplan creation 有权
标题翻译：在建立平面布置图时，将单元格放置在IC中的过程和装置
公开(公告)号：US20050091625A1
公开(公告)日：2005-04-28
申请号：US10694208
申请日：2003-10-27
申请人： Alexander Andreev , Andrey Nikitin , Igor Vikhliantsev
发明人： Alexander Andreev , Andrey Nikitin , Igor Vikhliantsev
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5072
摘要： Objects are placed in a rectangle and their coordinates of the objects and are adjusted to establish a substantially uniform density of objects in the rectangle. The evaluation of coordinates is performed by placing the wires between cells coordinates and adjusting the cell coordinates to connect the cells to the wires. The substantially uniform density is achieved by dividing the rectangle into first and second rectangles having equal free areas and into third and fourth rectangles having equal areas of objects. The coordinates of the objects are adjusted based on boundaries between the first and second rectangles and between the third and fourth rectangles.
摘要翻译：将对象放置在矩形中，并且对象的坐标进行调整，以在矩形中建立大致均匀的对象密度。坐标的评估是通过将电线放在单元之间进行坐标并调整单元坐标来连接单元与导线。通过将矩形分成具有相等空闲区域的第一和第二矩形以及具有相同面积的物体的第三和第四矩形来实现基本上均匀的密度。基于第一和第二矩形之间以及第三和第四矩形之间的边界来调整对象的坐标。

32. 发明申请

US20050149302A1 Method for evaluating logic functions by logic circuits having optimized number of and/or switches 失效
标题翻译：用于通过具有优化的数量和/或开关的逻辑电路来评估逻辑功能的方法
公开(公告)号：US20050149302A1
公开(公告)日：2005-07-07
申请号：US11055752
申请日：2005-02-10
申请人： Andrey Nikitin , Alexander Andreev
发明人： Andrey Nikitin , Alexander Andreev
IPC分类号： G06F17/10 , G06F17/50
CPC分类号： G06F17/505
摘要： A method for creating a logic circuit with an optimized number of AND/OR switches, which evaluates a logic function defined in a high-level description. Through analyzing the dependency relationship among operators used to define the logic function, the present invention may simplify the functional steps used in the high-level description to define the logic function and thus create a logic circuit with an optimized number of AND/OR switches.
摘要翻译：一种用于创建具有优化数量的AND / OR开关的逻辑电路的方法，其评估在高级描述中定义的逻辑功能。通过分析用于定义逻辑功能的运算符之间的依赖关系，本发明可以简化用于定义逻辑功能的高级描述中使用的功能步骤，从而创建具有优化数量的AND / OR开关的逻辑电路。

33. 发明申请

US20050066321A1 Parallel processor language, method for translating C++ programs into this language, and method for optimizing execution time of parallel processor programs 失效
标题翻译：并行处理器语言，将C ++程序转换成该语言的方法，以及优化并行处理器程序执行时间的方法
公开(公告)号：US20050066321A1
公开(公告)日：2005-03-24
申请号：US10667812
申请日：2003-09-22
申请人： Andrey Nikitin , Alexander Andreev
发明人： Andrey Nikitin , Alexander Andreev
IPC分类号： G06F9/44 , G06F9/45 , G06F9/46
CPC分类号： G06F8/443 , G06F8/314 , G06F8/51
摘要： The present invention is directed to a parallel processor language, a method for translating C++ programs into a parallel processor language, and a method for optimizing execution time of a parallel processor program. In an exemplary aspect of the present invention, a parallel processor program for defining a processor integrated circuit includes a plurality of processor commands with addresses. The plurality of processor commands may includes a starting processor command, and each of the plurality of processor commands includes one or more subcommands. When the processor integrated circuit executes the parallel processor program, the processor integrated circuit executes the staring processor command first and then executes the rest of the plurality of processor commands based on an order of the addresses. Moreover, when the processor integrated circuit executes a parallel processor command, the processor integrated circuit executes all subcommands included in the parallel processor command in parallel in one clock cycle.
摘要翻译：本发明涉及并行处理器语言，用于将C ++程序转换为并行处理器语言的方法以及用于优化并行处理器程序的执行时间的方法。在本发明的示例性方面，用于定义处理器集成电路的并行处理器程序包括具有地址的多个处理器命令。多个处理器命令可以包括起始处理器命令，并且多个处理器命令中的每一个包括一个或多个子命令。当处理器集成电路执行并行处理器程序时，处理器集成电路首先执行起始处理器命令，然后基于地址的顺序执行多个处理器命令中的其余部分。此外，当处理器集成电路执行并行处理器命令时，处理器集成电路在一个时钟周期内并行地执行并行处理器命令中包括的所有子命令。

34. 发明申请

US20050013155A1 Method and apparatus of IC implementation based on C++ language description 失效
标题翻译：基于C ++语言描述的IC实现方法和装置
公开(公告)号：US20050013155A1
公开(公告)日：2005-01-20
申请号：US10621737
申请日：2003-07-17
申请人： Andrey Nikitin , Alexander Andreev
发明人： Andrey Nikitin , Alexander Andreev
IPC分类号： G06F17/50 , G11C11/22
CPC分类号： G06F17/5022
摘要： The present invention is directed to a method and apparatus of IC implementation based on a C++ language description. In an exemplary aspect of the present invention, a method for evaluating a C++ description by an IC includes the following steps. First, a C++ description including a C++ program is provided. Then, the C++ program is stored in a first memory module (e.g., a ROM, or the like) of an IC. Next, a scalar input and/or an input array may be provided to the IC. Then, the C++ program may be executed by a control device module of the IC. Next, a scalar output and/or an output array may be read from the IC.
摘要翻译：本发明涉及基于C ++语言描述的IC实现的方法和装置。在本发明的一个示例性方面，用于通过IC评估C ++描述的方法包括以下步骤。首先，提供包括C ++程序的C ++描述。然后，C ++程序被存储在IC的第一存储器模块（例如，ROM等中）中。接下来，可以向IC提供标量输入和/或输入阵列。然后，C ++程序可以由IC的控制装置模块执行。接下来，可以从IC读取标量输出和/或输出阵列。

35. 发明申请

US20070094633A1 Method and system for mapping netlist of integrated circuit to design 失效
标题翻译：将集成电路网表映射到设计的方法和系统
公开(公告)号：US20070094633A1
公开(公告)日：2007-04-26
申请号：US11257289
申请日：2005-10-24
申请人： Alexander Andreev , Pavel Panteleev , Andrey Nikitin
发明人： Alexander Andreev , Pavel Panteleev , Andrey Nikitin
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/64
摘要： The present invention provides a method for mapping a netlist of an integrated circuit to a design. The method includes steps as follows. Chaos algorithm is used to obtain most favorable places in the design for cells from the netlist. Kuhn's algorithm is utilized to assign each cell of the netlist a cell in a template so that, for each cell of the netlist, its place in the template is as close as possible to its place obtained by the chaos algorithm. Simulating annealing optimization technique is applied to reduce a sum of wire length of the design.
摘要翻译：本发明提供了一种用于将集成电路的网表映射到设计的方法。该方法包括以下步骤。混沌算法用于从网表中为单元格设计获得最有利的位置。 Kuhn算法用于将网表中的每个单元格分配给模板中的单元，使得对于网表的每个单元，其在模板中的位置尽可能靠近其通过混沌算法获得的位置。应用模拟退火优化技术减少设计线长度的总和。

36. 发明授权

US07193905B1 RRAM flipflop rcell memory generator 有权
标题翻译： RRAM触发器rcell存储器发生器
公开(公告)号：US07193905B1
公开(公告)日：2007-03-20
申请号：US11259228
申请日：2005-10-25
申请人： Alexander Andreev , Sergei Gashkov , Oleg B. Sedelev , Andrey Nikitin
发明人： Alexander Andreev , Sergei Gashkov , Oleg B. Sedelev , Andrey Nikitin
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C11/418 , G11C8/10
摘要： An RRAM flip-flop rcell memory of the type having a write address decoder, a read address decoder, a set of n flip flops, one AND gate associated with each flip flop in the set, a set of w OR gates where each of the w OR gates in the set has n inputs, the improvement comprising only one write address decoder, and replacing the read address decoder and the set of AND gates and the set of OR gates with no more than one multiplexor, thereby providing a reduction in a path length from an rcell memory input to an rcell memory output and thereby improving timing of the rcell memory, while reducing fanout size of the rcell. In a preferred embodiment, the multiplexor includes fewer than w OR gates, and fewer than n AND gates, and two decoders, which are commonly connected to outputs of the n flip flops.
摘要翻译：具有写地址解码器，读地址解码器，一组n个触发器，与该组中的每个触发器相关联的一个与门的RRAM触发器rcell存储器，一组w OR门，其中每个该组中的w或门具有n个输入，改进仅包括一个写地址解码器，并且用不多于一个多路复用器替换读地址解码器和与门组和OR门组，从而提供从rcell存储器输入到rcell存储器输出的路径长度，从而提高rcell存储器的定时，同时减少rcell的扇出大小。在优选实施例中，多路复用器包括通常连接到n个触发器的输出的少于或几个门，以及少于n个与门和两个解码器。

37. 发明授权

US07356743B2 RRAM controller built in self test memory 失效
标题翻译： RRAM控制器内置自检内存
公开(公告)号：US07356743B2
公开(公告)日：2008-04-08
申请号：US11256829
申请日：2005-10-24
申请人： Andrey Nikitin , Ilya V. Neznanov , Alexander Andreev
发明人： Andrey Nikitin , Ilya V. Neznanov , Alexander Andreev
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C29/16 , G11C2029/1208
摘要： An RRAM design having linear BIST memory and rectangular BIST memory, the improvement comprising at least one of the linear BIST memory and the rectangular BIST memory formed only of flipflops and logic cells.
摘要翻译：具有线性BIST存储器和矩形BIST存储器的RRAM设计，改进包括仅由触发器和逻辑单元形成的线性BIST存储器和矩形BIST存储器中的至少一个。

38. 发明申请

US20070230621A1 DIGITAL GAUSSIAN NOISE SIMULATOR 有权
公开(公告)号：US20070230621A1
公开(公告)日：2007-10-04
申请号：US11758975
申请日：2007-06-06
申请人： Andrey Nikitin , Alexander Andreev , Igor Vikhliantsev
发明人： Andrey Nikitin , Alexander Andreev , Igor Vikhliantsev
IPC分类号： H03K9/00
CPC分类号： G06F17/18
摘要： A Gaussian noise is simulated by discrete analogue ri,j. A first parameter α and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on α, i and j. The discrete analogue ri,j is based on a respective si,j. Examples are given of α = 2 B - A 2 B and D>i≧0 and 2C>j≧0, where B≧0, 2B>A>0, C≧1 and D≧1, and magnitude s i , j = 1 - α i + α i · 1 - α 2 C · j ⁢ ⁢ or ⁢ ⁢ s D - 1 , j = 1 - α D - 1 + α D - 1 · 1 2 C · j . In some embodiments, a segment is defined based on α and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.

39. 发明申请

US20070091702A1 RRAM controller built in self test memory 失效
标题翻译： RRAM控制器内置自检内存
公开(公告)号：US20070091702A1
公开(公告)日：2007-04-26
申请号：US11256829
申请日：2005-10-24
申请人： Andrey Nikitin , Ilya Neznanov , Alexander Andreev
发明人： Andrey Nikitin , Ilya Neznanov , Alexander Andreev
IPC分类号： G11C7/02
CPC分类号： G11C29/12 , G11C29/16 , G11C2029/1208
摘要： An RRAM design having linear BIST memory and rectangular BIST memory, the improvement comprising at least one of the linear BIST memory and the rectangular BIST memory formed only of flipflops and logic cells.
摘要翻译：具有线性BIST存储器和矩形BIST存储器的RRAM设计，改进包括仅由触发器和逻辑单元形成的线性BIST存储器和矩形BIST存储器中的至少一个。

40. 发明申请

US20050240889A1 Process and apparatus for placing cells in an IC floorplan 有权
标题翻译：将电池放置在IC平面图中的工艺和设备
公开(公告)号：US20050240889A1
公开(公告)日：2005-10-27
申请号：US10830542
申请日：2004-04-23
申请人： Alexander Andreev , Andrey Nikitin , Igor Vikhliantsev
发明人： Alexander Andreev , Andrey Nikitin , Igor Vikhliantsev
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5072
摘要： Cells are placed into an integrated circuit floorplan by creating clusters of cells in modules, each cluster being composed of cells in a path connected to at least one flip-flop in the module, or of cells that are not in a path connected to any flip-flop. Regions are defined in the floorplan for placement of modules, and the clusters are placed into optimal locations in modules and placing the modules into optimal locations in the regions. T coordinates for the wires, modules and clusters are selectively recalculated. The clusters are moved in the floorplan for more uniform density, and the modules are assigned to regions based on module coordinates.
摘要翻译：通过在模块中创建单元格群，将单元放置在集成电路平面布置图中，每个簇由连接到模块中的至少一个触发器的路径中的单元或者不连接到任何翻转的路径的单元组成 -flop。区域在布局图中定义，用于放置模块，并将集群放置在模块中的最佳位置，并将模块放置在区域中的最佳位置。有选择地重新计算电线，模块和集群的T坐标。群集在平面图中移动以获得更均匀的密度，并且将模块分配给基于模块坐标的区域。

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