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31. 发明授权

US09411527B2 Storage system and data management method 有权
公开(公告)号：US09411527B2
公开(公告)日：2016-08-09
申请号：US14721608
申请日：2015-05-26
申请人： Hitachi, Ltd.
发明人： Hiroaki Akutsu , Junji Ogawa
IPC分类号： G06F11/00 , G06F3/06 , G06F11/10
CPC分类号： G06F3/0619 , G06F3/0665 , G06F3/0689 , G06F11/1092 , G06F2003/0692
摘要： Storage system comprises a second storage apparatus, which is coupled to multiple first storage apparatuses and is of a different type from the first storage apparatuses, and a first control device, which exists either inside or outside of the second storage apparatus. Row of stripes comprising multiple data elements obtained by segmenting a prescribed data unit, and a redundancy code for rebuilding the data elements, is distributively stored in multiple first storage apparatuses, which are more numerous than the total number of stripe data elements, which are either the data elements or redundancy code, in the row of stripes. The row of stripes is configured to enable the rebuilding of the stripe data elements even when a failure has occurred in up to a prescribed allowable number, which is two or more, of the first storage apparatuses storing the stripe data elements of the relevant row of stripes.

32. 发明授权

US09367469B2 Storage system and cache control method 有权
标题翻译：存储系统和缓存控制方法
公开(公告)号：US09367469B2
公开(公告)日：2016-06-14
申请号：US13816656
申请日：2013-01-31
申请人： Hitachi, Ltd.
发明人： Junji Ogawa , Akifumi Suzuki
IPC分类号： G06F12/08 , G06F11/10
CPC分类号： G06F12/0871 , G06F11/1076 , G06F2211/1009 , G06F2211/1059 , G06F2212/7202 , G06F2212/7211
摘要： A cache memory comprises a cache controller and a nonvolatile semiconductor memory as a storage medium. The nonvolatile semiconductor memory comprises multiple blocks, which are data erase units, and each block comprises multiple pages, which are data write and read units. The cache controller receives data and attribute information of the data, and, based on the received attribute information and attribute information of the data stored in the multiple blocks, selects a storage-destination block for storing the received data, and writes the received data to a page inside the selected storage-destination block.
摘要翻译：高速缓冲存储器包括作为存储介质的高速缓存控制器和非易失性半导体存储器。非易失性半导体存储器包括作为数据擦除单元的多个块，并且每个块包括作为数据写入和读取单元的多个页面。高速缓存控制器接收数据的数据和属性信息，并且基于接收的属性信息和存储在多个块中的数据的属性信息，选择用于存储接收到的数据的存储目的地块，并将接收的数据写入所选存储目的地块内的页面。

33. 发明授权

US09343153B2 De-duplication in flash memory module 有权
标题翻译：闪存模块中的重复数据删除
公开(公告)号：US09343153B2
公开(公告)日：2016-05-17
申请号：US14798888
申请日：2015-07-14
申请人： HITACHI, LTD.
发明人： Atsushi Kawamura , Junji Ogawa
IPC分类号： G06F12/00 , G11C16/04 , G06F12/02 , G06F3/06 , G06F11/10
CPC分类号： G11C16/0483 , G06F3/0608 , G06F3/0616 , G06F3/0641 , G06F3/0679 , G06F3/0688 , G06F11/1044 , G06F11/108 , G06F12/0246 , G06F2212/7202 , G11C16/04
摘要： Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area.
摘要翻译：通过使用与每个数据不同的代码分配的数据进行解除复制来提高数据容量效率。一种存储装置，包括配备有一个或多个闪速存储器模块的闪速存储器控制装置，其中所述闪速存储器模块包括用于提供存储区域的至少一个闪速存储器芯片，以及用于控制对包括用户数据的数据的写入/读取的控制器，伴随着闪存芯片所提供的存储区域的用户数据的保证码，其中控制器分别将具有公共用户数据的多个数据划分成用户数据和保证码，存储用户数据之一在所述存储区域的预定单位的区域中，在所述存储区域的预定单位的区域中链接并存储伴随所述多个用户数据的每个所述保证码。

34. 发明授权

US09128847B2 Cache control apparatus and cache control method 有权
标题翻译：缓存控制装置和缓存控制方法
公开(公告)号：US09128847B2
公开(公告)日：2015-09-08
申请号：US13695754
申请日：2012-10-18
申请人： Hitachi, Ltd.
发明人： Yuji Ito , Junji Ogawa , Hideyuki Koseki
IPC分类号： G06F3/0484 , G06F7/48 , G06F7/64 , G06F12/08 , G06F12/02
CPC分类号： G06F12/0811 , G06F12/0246 , G06F12/0868 , G06F12/0897 , G06F2212/225 , G06F2212/7208
摘要： A cache control apparatus comprises a primary cache part, a secondary cache part for caching data destaged from the primary cache part, and a controller connected to the primary cache part and to the secondary cache part. The secondary cache part has a first storage part and a second storage part having a lifetime longer than that of the first storage part. The controller determines whether the data destaged from the primary cache part is to be stored in the first storage part or the second storage part in the secondary cache part, based on a use state indicating whether or not the data has been updated, and stores the data in the first storage part or the second storage part determined.
摘要翻译：高速缓存控制装置包括主缓存部分，用于高速缓存从主高速缓存部分迁移的数据的二级高速缓存部分，以及连接到主高速缓存部分和辅助高速缓存部分的控制器。二级缓存部具有比第一存储部的寿命长的第一存储部和第二存储部。基于指示数据是否被更新的使用状态，控制器确定从主缓存部分发送的数据是否要被存储在次高速缓存部分中的第一存储部分或第二存储部分中，并且存储确定第一存储部分或第二存储部分中的数据。

35. 发明申请

US20150106555A1 NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM 审中-公开
标题翻译：非易失性半导体存储系统
公开(公告)号：US20150106555A1
公开(公告)日：2015-04-16
申请号：US14573269
申请日：2014-12-17
申请人： Hitachi, Ltd.
发明人： ATSUSHI ISHIKAWA , Koji Sonoda , Go Uehara , Junji Ogawa , Hideyuki Koseki
IPC分类号： G06F3/06 , G06F13/16 , G06F13/40
CPC分类号： G06F3/0608 , G06F3/0626 , G06F3/0635 , G06F3/0647 , G06F3/0658 , G06F3/0685 , G06F3/0688 , G06F12/0246 , G06F13/16 , G06F13/1684 , G06F13/4022
摘要： A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips.
摘要翻译：非易失性半导体存储系统具有多个非易失性半导体存储介质，具有耦合到多个非易失性半导体存储介质的介质接口组（一个或多个接口器件）和多个开关的控制电路。介质接口组和多个开关经由数据总线耦合，并且每个开关和两个或更多个非易失性芯片中的每一个经由数据总线耦合。该开关被配置为切换耦合到媒体接口组的数据总线与耦合到耦合到该开关的多个非易失性芯片中的任何一个的数据总线之间的耦合。控制电路将写目标数据分成多个数据元，通过控制多个开关切换耦合，并将多个数据元素分配发送到多个非易失性芯片。

36. 发明授权

US10803972B2 Flash memory module, storage system, and method of controlling flash memory 有权
公开(公告)号：US10803972B2
公开(公告)日：2020-10-13
申请号：US16327272
申请日：2017-03-06
申请人： Hitachi, Ltd.
发明人： Akifumi Suzuki , Junji Ogawa
IPC分类号： H03M13/00 , G11C29/52 , G06F3/06 , G11C29/42 , G06F11/30 , G06F11/10 , G11C29/50 , G11C29/04
摘要： A flash memory module includes a flash memory and a controller. The controller acquires information indicating reliability of monitoring target data of the flash memory, specifies a first cell, which is a cell having a threshold voltage level lower than a threshold voltage level of a corresponding cell in expected value data obtained by correcting an error bit of the monitoring target data, among cells in which error bits have occurred of the monitoring target data when it is determined that the reliability indicated by the acquired information is lower than a predetermined condition, and transmits rewrite correction target cell data, which is data corresponding to data of the first cell in the expected value data, to the flash memory. The flash memory injects an electron into the first cell based on a threshold voltage indicated by the rewrite correction target cell data.

37. 发明授权

US10444992B2 Storage device, apparatus having storage device, and storage control method 有权
公开(公告)号：US10444992B2
公开(公告)日：2019-10-15
申请号：US15110310
申请日：2014-02-26
申请人： HITACHI, LTD.
发明人： Nagamasa Mizushima , Junji Ogawa , Atsushi Kawamura
IPC分类号： G06F3/00 , G06F3/06 , G11C7/10
摘要： A storage device provides a logical space based on a storage medium that is configured by a plurality of logical areas to the higher-level apparatus, and a base data range exists in the storage medium for each logical area. The storage device reads the base data from the base data range that is corresponded to a write destination logical area to which the write destination logical address belongs, and creates difference data that is an exclusive OR of first data that is the base data and second data that is any one of data based on write data and the write data. The storage device creates compressed difference data by compressing the difference data, writes the compressed difference data to the storage medium, and associates a difference data range that is a range in which the compressed difference data has been written with the write destination logical area.

38. 发明授权

US10102060B2 Storage apparatus and data control method of storing data with an error correction code 有权
公开(公告)号：US10102060B2
公开(公告)日：2018-10-16
申请号：US14762841
申请日：2013-08-30
申请人： Hitachi, Ltd.
发明人： Hideyuki Koseki , Takashi Tsunehiro , Junji Ogawa , Nagamasa Mizushima , Atsushi Kawamura
IPC分类号： G06F11/10 , G11C29/52 , G06F3/06 , G06F12/04 , G06F12/16 , G06F12/02
摘要： In a storage apparatus including a storage medium including a plurality of pages as a unit of reading and writing data, a first data block including a data block received from a higher-level device is generated, a second data block of a predetermined size including one or more undivided first data blocks is generated, a third data block in which a correction code is added to the second data block is generated, the third data block is stored in a page buffer, and one or more of the third data blocks stored in the page buffer is written in a page, which is a write destination, out of the pages of the storage medium.

39. 发明授权

US09778986B2 Storage system 有权
公开(公告)号：US09778986B2
公开(公告)日：2017-10-03
申请号：US14426716
申请日：2014-03-28
申请人： Hitachi, Ltd.
发明人： Tomohiro Yoshihara , Akira Yamamoto , Shigeo Homma , Junji Ogawa
IPC分类号： G11C29/00 , G06F11/10 , G06F3/06
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0688 , G06F3/0689
摘要： The storage system according to the present invention comprises a controller, and multiple storage device constituting a RAID group. When storing write data to multiple discontinuous areas within stripes of a storage device, the storage system transmits a new data transmission command containing information for specifying the multiple discontinuous areas and a write data to the storage device, and thereafter, receives an intermediate parity generated from multiple write data and data before update of the multiple write data from the storage device, and then transmits the received intermediate parity and an intermediate parity transmission command to the storage device storing the parity. Thereafter, a data commitment command containing information for specifying multiple discontinuous areas is transmitted to multiple storage devices, and the storage device storing the parity generates a parity after update from the received intermediate parity and a parity before update corresponding to the intermediate parity, and stores the parity after update in a storage media.

40. 发明授权

US09727246B2 Memory device, computer system, and method of controlling memory device 有权
公开(公告)号：US09727246B2
公开(公告)日：2017-08-08
申请号：US14764659
申请日：2013-05-22
申请人： Hitachi, Ltd.
发明人： Satoru Watanabe , Junji Ogawa , Nagamasa Mizushima
IPC分类号： G06F12/00 , G06F3/06 , G06F12/04 , G06F12/02
CPC分类号： G06F3/0608 , G06F3/06 , G06F3/064 , G06F3/0688 , G06F12/0246 , G06F12/04 , G06F2212/401 , G06F2212/7202
摘要： An example of the invention is a memory device including a controller and a plurality of randomly accessible memories that are capable of storing user data from a host. The controller includes data management information managing correspondence relations between address areas to be designated by the host and the plurality of memories, and compression policy management information managing associations of the address areas to be designated by the host with priorities in compressing user data to be stored in the plurality of memories. The controller is configured to determine a compression policy associated with a designated address area included in an access request from the host based on a priority associated with the designated address area and information on free space of the plurality of memories.

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