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31. 发明申请

US20160350230A1 APPARATUSES AND METHODS FOR COMPUTE ENABLED CACHE 审中-公开
标题翻译：用于计算机启动的缓存的设备和方法
公开(公告)号：US20160350230A1
公开(公告)日：2016-12-01
申请号：US15066488
申请日：2016-03-10
申请人： Micron Technology, Inc.
发明人： Richard C. Murphy
IPC分类号： G06F12/08 , G06F9/30 , G11C11/406 , G11C7/10
CPC分类号： G06F12/0864 , G06F9/30036 , G06F12/0811 , G06F2212/283 , G06F2212/6032 , G11C7/1006 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C19/00
摘要： The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.
摘要翻译：本公开包括用于计算使能的高速缓存的装置和方法。示例性设备包括计算组件，存储器和耦合到存储器的控制器。所述控制器被配置为在块选择和子选择作为元数据操作到高速缓存行以控制高速缓存行在存储器中的放置以允许计算使能的高速缓存。

32. 发明申请

US20160062692A1 APPARATUSES AND METHODS FOR DETERMINING POPULATION COUNT 审中-公开
标题翻译：用于确定人口计数的装置和方法
公开(公告)号：US20160062692A1
公开(公告)日：2016-03-03
申请号：US14833796
申请日：2015-08-24
申请人： Micron Technology, Inc.
发明人： Timothy P. Finkbeiner , Glen E. Hush , Richard C. Murphy
IPC分类号： G06F3/06
CPC分类号： G11C16/26 , G11C7/06 , G11C7/065 , G11C7/1006 , G11C7/1009 , G11C7/12
摘要： The present disclosure includes apparatuses and methods related to determining population count. An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a controller configured to cause: summing, in parallel, of data values corresponding to respective ones of a plurality of first vectors stored in memory cells of the array as a data value sum representing a population count thereof, wherein a second vector is stored as the plurality of first vectors, and wherein each first vector of the plurality of first vectors is stored in respective memory cells of the array that are coupled to a respective sense line of a plurality of sense lines; and iteratively summing, in parallel, of data value sums corresponding to the plurality of first vectors to provide a single data value sum corresponding to the second vector.
摘要翻译：本公开包括与确定人口数量有关的装置和方法。示例性设备包括耦合到感测电路的存储器单元的阵列。该装置可以包括：控制器，其被配置为：并行地对应于存储在阵列的存储器单元中的多个第一向量中的相应的数据值作为表示其总数的数据值和，其中第二向量被存储为多个第一矢量，并且其中多个第一矢量中的每个第一矢量被存储在阵列的相应的存储单元中，耦合到多个感测线的相应感测线; 并且对与多个第一向量相对应的数据值和迭代地求和，以提供对应于第二向量的单个数据值和。

33. 发明申请

US20230100557A1 HOST-BASED ERROR CORRECTION 有权
公开(公告)号：US20230100557A1
公开(公告)日：2023-03-30
申请号：US17991287
申请日：2022-11-21
申请人： Micron Technology, Inc.
发明人： Reshmi Basu , Richard C. Murphy
IPC分类号： G06F11/10 , G06F11/07 , G06F3/06 , G06F11/20
摘要： Systems, apparatuses, and methods related to host-based error correction are described. Error correction operations can be performed on a host computing system as opposed to on a memory system. For instance, data containing erroneous bits can be transferred from a memory system to a host computing system and error correction operations can be performed using circuitry resident on the host computing system. In an example, a method can include receiving, by a host computing system, data that comprises a plurality of uncorrected bits from a memory system coupleable to the host computing system, determining an acceptable error range for the data based at least in part on an application associated with the data, and performing, using error correction logic resident on the host computing system, an initial error correction operation on the data based at least in part on the acceptable error range.

34. 发明授权

US11594274B2 Processing in memory (PIM)capable memory device having timing circuity to control timing of operations 有权
公开(公告)号：US11594274B2
公开(公告)日：2023-02-28
申请号：US17157447
申请日：2021-01-25
申请人： Micron Technology, Inc.
发明人： Richard C. Murphy
IPC分类号： G11C7/08 , G11C11/4091 , G11C11/4076 , G11C7/10 , G11C11/4093 , G11C11/4096 , G06F3/06
摘要： Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.

35. 发明申请

US20220392499A1 INTERFACE PROTOCOL CONFIGURATION FOR MEMORY 有权
公开(公告)号：US20220392499A1
公开(公告)日：2022-12-08
申请号：US17888457
申请日：2022-08-15
申请人： Micron Technology, Inc.
发明人： Richard C. Murphy , Glen E. Hush , Honglin Sun
IPC分类号： G11C7/10 , G06F13/38 , G06F9/30 , G06F9/54
摘要： Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing pins of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided through the pins of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.

36. 发明授权

US11482260B2 Apparatuses and methods for scatter and gather 有权
公开(公告)号：US11482260B2
公开(公告)日：2022-10-25
申请号：US17215581
申请日：2021-03-29
申请人： Micron Technology, Inc.
发明人： Jason T. Zawodny , Kelley D. Dobelstein , Timothy P. Finkbeiner , Richard C. Murphy
IPC分类号： G11C7/10 , G11C11/4096 , G11C11/4091 , G11C11/408 , G06F3/06 , G11C8/12 , G11C7/06
摘要： The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

37. 发明申请

US20220326889A1 ASYNCHRONOUS PROCESS TOPOLOGY IN A MEMORY DEVICE 有权
公开(公告)号：US20220326889A1
公开(公告)日：2022-10-13
申请号：US17850595
申请日：2022-06-27
申请人： Micron Technology, Inc.
发明人： Glen E. Hush , Richard C. Murphy , Honglin Sun
IPC分类号： G06F3/06 , G06F1/12
摘要： Apparatuses and methods can be related to generating an asynchronous process topology in a memory device. The topology can be generated based on the results of a number of processes. The processes can be asynchronous given that the processing resources that implement the processes do not use a clock signal to generate the topology.

38. 发明授权

US11449269B2 Edge compute components under a memory array 有权
公开(公告)号：US11449269B2
公开(公告)日：2022-09-20
申请号：US16936079
申请日：2020-07-22
申请人： Micron Technology, Inc.
发明人： Glen E. Hush , Richard C. Murphy , Honglin Sun
IPC分类号： G06F3/06 , G06F3/00
摘要： Apparatuses and methods can be related to implementing edge compute components in a memory array. Compute components can be implemented under a memory array. Implementing compute components under a memory array can limit control access to the compute components due to die space utilized by the compute components. A portion of the compute components (e.g., compute components on the edge) may have control access that is not available to the remainder of the compute components.

39. 发明申请

US20220269509A1 GENERATING AND EXECUTING A CONTROL FLOW 有权
公开(公告)号：US20220269509A1
公开(公告)日：2022-08-25
申请号：US17743062
申请日：2022-05-12
申请人： Micron Technology, Inc.
发明人： Kyle B. Wheeler , Richard C. Murphy , Troy A. Manning , Dean A. Klein
IPC分类号： G06F9/38 , G06F15/78 , G11C7/06 , G11C7/10 , G11C11/408 , G11C11/4096
摘要： Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

40. 发明申请

US20220261359A1 MEMORY MODULE DATA OBJECT PROCESSING SYSTEMS AND METHODS 有权
公开(公告)号：US20220261359A1
公开(公告)日：2022-08-18
申请号：US17733320
申请日：2022-04-29
申请人： Micron Technology, Inc.
发明人： Richard C. Murphy
IPC分类号： G06F12/14 , G06F12/0813 , G06F9/455
摘要： The present disclosure provides methods, apparatus, and systems for implementing and operating a memory module, for example, in a computing that includes a network interface, which may be coupled to a network to enable communication with a client device, and host processing circuitry, which may be coupled to the network interface via a system bus and programmed to perform first data processing operations based on user inputs received from the client device. The memory module may be coupled to the system bus and include memory devices and a memory controller coupled to the memory devices via an internal bus. The memory controller may include memory processing circuitry programmed to perform a second data processing operation that facilitates performance of the first data processing operations by the host processing circuitry based on context of the data block indicated by the metadata.

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