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31. 发明授权

US09484811B2 Integrated circuit comprising voltage modulation circuitry and method threfor 有权
标题翻译：包括电压调制电路和方法的集成电路
公开(公告)号：US09484811B2
公开(公告)日：2016-11-01
申请号：US13378239
申请日：2009-07-16
申请人： Franck Galtie , Philippe Goyhenetche , Eric Rolland
发明人： Franck Galtie , Philippe Goyhenetche , Eric Rolland
IPC分类号： H02M3/156 , H02M7/04 , H02M3/158 , H02M3/157
CPC分类号： H02M3/156 , H02M3/157 , H02M3/158 , H02M7/04
摘要： An integrated circuit comprising voltage modulation circuitry arranged to convert an input voltage level at an input node to an output voltage level at an output node. The voltage modulation circuitry comprises a switching element arranged to connect the input node to the output node when in an ON condition, and switching control module operably coupled to the switching element and arranged to control the connection of the input node to the output node by the switching element in accordance with a switching frequency. The voltage modulation circuitry further comprises frequency control module operably coupled to the switching control module and arranged to receive an indication of the input voltage level at the input node, and to configure the switching frequency based at least partly on the input voltage level indication.
摘要翻译：一种集成电路，包括电压调制电路，其被布置成将输入节点处的输入电压电平转换为输出节点处的输出电压电平。电压调制电路包括开关元件，其被布置为在处于导通状态时将输入节点连接到输出节点，以及切换控制模块，其可操作地耦合到开关元件并被布置成通过所述输入节点与所述输出节点的连接来控制开关元件。电压调制电路还包括可操作地耦合到开关控制模块并被布置成接收输入节点处的输入电压电平的指示并且至少部分地基于输入电压电平指示来配置开关频率的频率控制模块。

32. 发明授权

US09484320B2 Vertically packaged integrated circuit 有权
标题翻译：垂直封装的集成电路
公开(公告)号：US09484320B2
公开(公告)日：2016-11-01
申请号：US13458224
申请日：2012-04-27
申请人： Christopher W. Argento
发明人： Christopher W. Argento
IPC分类号： H01L23/495 , H01L23/00 , H01L23/433
CPC分类号： H01L24/49 , H01L23/4334 , H01L23/4951 , H01L23/49517 , H01L23/49537 , H01L23/49568 , H01L24/16 , H01L24/48 , H01L24/73 , H01L2224/13009 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/49175 , H01L2224/4918 , H01L2224/73253 , H01L2924/00014 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A device comprises a semiconductor package including a first integrated circuit (IC) die including a plurality of through silicon vias (TSVs). The TSVs are formed of conductive material that extend through the first IC die from an outer surface on a first side of the die to an outer surface of a second side of the die. The package further includes first electrical connections contacting the first side of the first IC die, and second electrical connections contacting the second side of the first IC die. The first electrical connections are independent of the second electrical connections. Molding compound encapsulates the first IC die and the first and second electrical connections. The semiconductor package is mounted on a substrate so that the first and second sides of the IC die are oriented perpendicular to the substrate.
摘要翻译：一种器件包括半导体封装，其包括具有多个穿通硅通孔（TSV）的第一集成电路（IC）管芯。 TSV由导电材料形成，该导电材料从模具的第一侧的外表面延伸穿过第一IC管芯到模具的第二侧的外表面。该封装还包括接触第一IC管芯的第一侧的第一电连接和接触第一IC管芯的第二侧的第二电连接。第一电连接与第二电连接无关。模制化合物封装第一IC芯片和第一和第二电连接。将半导体封装安装在基板上，使得IC管芯的第一和第二侧面垂直于衬底取向。

33. 发明授权

US09484289B2 Semiconductor device with heat spreader 有权
标题翻译：带散热器的半导体器件
公开(公告)号：US09484289B2
公开(公告)日：2016-11-01
申请号：US14462567
申请日：2014-08-19
申请人： You Ge , Meng Kong Lye , Penglin Mei
发明人： You Ge , Meng Kong Lye , Penglin Mei
IPC分类号： H01L23/10 , H01L23/495 , H01L23/36 , H01L23/433
CPC分类号： H01L23/49568 , H01L23/36 , H01L23/4334 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014
摘要： A semiconductor device includes a package body, a semiconductor die embedded in the package body and a heat spreader attached to a top surface of the package body and spaced from semiconductor die. The heat spreader may be formed of solder that is melted within a recess in the top surface of the package body.
摘要翻译：半导体器件包括封装主体，嵌入封装主体中的半导体管芯和附接到封装主体的顶表面并与半导体管芯间隔开的散热器。散热器可以由在封装主体的顶表面中的凹部内熔化的焊料形成。

34. 发明授权

US09484222B2 Semiconductor devices, semiconductor device packages, and packaging techniques for impedance matching and/or low frequency terminations 有权
标题翻译：用于阻抗匹配和/或低频端接的半导体器件，半导体器件封装和封装技术
公开(公告)号：US09484222B2
公开(公告)日：2016-11-01
申请号：US14184266
申请日：2014-02-19
申请人： Freescale Semiconductor, Inc.
发明人： Hussain H. Ladhani , Lu Li , Mahesh K. Shah , Lakshminarayan Viswanathan , Michael E. Watts
IPC分类号： H01L23/02 , H01L27/08 , H01L21/48 , H03F3/193 , H03F3/21 , H01L25/00 , H01L23/66 , H03F1/56 , H03F3/195
CPC分类号： H01L21/4853 , H01L23/66 , H01L25/50 , H01L2223/6611 , H01L2223/6655 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H03F1/565 , H03F3/193 , H03F3/195 , H03F3/21 , H03F2200/423 , H03F2200/451 , H01L2924/00014
摘要： A semiconductor device, related package, and method of manufacturing same are disclosed. In at least one embodiment, the semiconductor device includes a radio frequency (RF) power amplifier transistor having a first port, a second port, and a third port. The semiconductor device also includes an output lead, a first output impedance matching circuit between the second port and the output lead, and a first additional circuit coupled between the output lead and a ground terminal. At least one component of the first additional circuit is formed at least in part by way of one or more of a plurality of castellations and a plurality of vias.
摘要翻译：公开了一种半导体器件，相关封装及其制造方法。在至少一个实施例中，半导体器件包括具有第一端口，第二端口和第三端口的射频（RF）功率放大器晶体管。半导体器件还包括输出引线，第二端口和输出引线之间的第一输出阻抗匹配电路，以及耦合在输出引线和接地端子之间的第一附加电路。第一附加电路的至少一个部件至少部分地通过多个城堡和多个通孔中的一个或多个形成。

35. 发明申请

US20160315617A1 LOW-VOLTAGE DIFFERENTIAL SIGNALING (DIFFERENTIAL SIGNALING) DRIVER CIRCUIT AND METHOD OF ENABLING AND DISABLING A DIFFERENTIAL SIGNALING DRIVER CIRCUIT 审中-公开
标题翻译：低电压差分信号（差分信号）驱动电路和启动和禁用差分信号驱动电路的方法
公开(公告)号：US20160315617A1
公开(公告)日：2016-10-27
申请号：US15035544
申请日：2013-11-28
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： ALEXEY MICHAILOVICH BALASHOV , ANDREY EVGENEVICH MALKOV
IPC分类号： H03K19/0185 , H03F1/02 , H03F3/45
CPC分类号： H03K19/018528 , H03F1/0222 , H03F1/0233 , H03F1/223 , H03F3/45381 , H03F3/45659 , H03F3/45946 , H03F2203/45418 , H03F2203/45424 , H03F2203/45431 , H03K19/00361 , H03K19/018521
摘要： A Low-Voltage Differential Signaling (differential signaling) driver circuit (10) comprising enable circuitry for enabling and disabling the differential signaling driver circuit (10) in accordance with an control signal is described. The differential signaling driver circuit (10) comprises: a differential output (12, 13) connected or connectable to a differential signaling receiver circuit via a differential transmission line; current control circuitry (14) for driving a signal current through the differential output (12, 13) in accordance with a driver signal; feedback circuitry (16) for driving the current control circuitry (14) to counteract a difference between a common mode voltage of the differential output (12, 13) and a reference voltage from a reference voltage provider; and the enable circuitry (18). The feedback circuitry (16) comprises a common mode node (20) for providing the common mode voltage (Vcm), a reference input (22) connected or connectable to the reference voltage provider, and a feedback input (24). The enable circuitry (18) is arranged to connect the feedback input (24) to the common mode node (20) when the differential signaling driver circuit (10) is in an enabled state and to the reference voltage provider when the differential signaling driver circuit (10) is in a disabled state. A method of enabling (5.1) and disabling (5.2) a Low-Voltage Differential Signaling (differential signaling) driver circuit (10) is also proposed.
摘要翻译：描述了包括使能电路的低电压差分信号（差分信号）驱动器电路（10），用于根据控制信号启用和禁用差分信号驱动器电路（10）。差分信号驱动器电路（10）包括：差分输出（12,13），经差分传输线路连接或连接到差分信号接收器电路; 电流控制电路（14），用于根据驱动器信号驱动通过差分输出（12,13）的信号电流; 反馈电路（16），用于驱动电流控制电路（14）以抵消差分输出（12,13）的共模电压与参考电压提供器的参考电压之间的差; 和使能电路（18）。反馈电路（16）包括用于提供共模电压（Vcm）的共模节点（20），连接或可连接到参考电压提供器的参考输入端（22）和反馈输入端（24）。使能电路（18）被布置成当差分信号驱动器电路（10）处于使能状态时将反馈输入（24）连接到共模节点（20），并且当差分信号驱动器电路（10）处于禁用状态。还提出了启用（5.1）和禁用（5.2）低电压差分信号（差分信令）驱动器电路（10）的方法。

36. 发明授权

US09479794B2 Resource efficient video processing via prediction error computational adjustments 有权
标题翻译：通过预测误差计算调整资源有效的视频处理
公开(公告)号：US09479794B2
公开(公告)日：2016-10-25
申请号：US11271693
申请日：2005-11-10
申请人： Zhong Li He , Yong Yan
发明人： Zhong Li He , Yong Yan
IPC分类号： H04B1/66 , H04N19/523 , H04N19/176 , H04N19/134 , H04N19/102 , H04N19/61 , H04N19/124 , H04N19/14 , H04N19/152 , H04N19/156 , H04N19/162
CPC分类号： H04N19/65 , H04N19/102 , H04N19/124 , H04N19/134 , H04N19/14 , H04N19/152 , H04N19/156 , H04N19/162 , H04N19/176 , H04N19/513 , H04N19/523 , H04N19/61
摘要： A video processing system dynamically adjusts video processing prediction error reduction computations in accordance with the amount of motion represented in a set of image data and/or available memory resources to store compressed video data. In at least one embodiment, video processing system adjusts utilization of prediction error computational resources based on the size of a prediction error between a first set of image data, such as current set of image data being processed, and a reference set of image data relative to an amount of motion in a current set of image data. Additionally, in at least one embodiment, the video processing adjusts utilization of prediction error computation resources based upon a fullness level of a data buffer relative to the amount of motion in the current set of image data.
摘要翻译：视频处理系统根据在一组图像数据和/或可用存储器资源中表示的运动量来动态地调整视频处理预测误差减少计算以存储压缩视频数据。在至少一个实施例中，视频处理系统基于第一组图像数据（例如正在处理的图像数据的当前集合）与相关图像数据的参考集合之间的预测误差的大小来调整预测误差计算资源的利用到当前图像数据集合中的运动量。另外，在至少一个实施例中，视频处理基于数据缓冲器相对于当前图像数据集合中的运动量的饱和度来调整预测误差计算资源的利用率。

37. 发明授权

US09479374B1 Digital front-end channelization device 有权
标题翻译：数字前端渠道化设备
公开(公告)号：US09479374B1
公开(公告)日：2016-10-25
申请号：US14880738
申请日：2015-10-12
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Roi Menahem Shor , Frederic Paul Fernez , Avraham Dov Gal , Peter Zahariev Rashev
IPC分类号： H04K1/02 , H04L27/26
CPC分类号： H04L27/2614 , H04L5/001 , H04L5/0064 , H04L5/0091 , H04L27/2624
摘要： A digital front end channelization device for one or more carrier signals comprises a per carrier section and a composite section. The composite section may include signal processing units, each of which may include an inverse Fourier transform unit for transforming a composite carrier signal into a time domain signal, a sample detection and selection unit for detecting and selecting a peak of the time domain signal, a clipping unit for clipping the time domain composite carrier signal to produce an error signal, a Fourier transform unit, for transforming the error signal into a frequency domain error signal, a frequency shaping unit for frequency shaping the frequency domain error signal, a summation unit for subtracting the frequency shaped frequency domain error signal from the composite carrier signal, and a phase selection unit for phase adjustment of the resulting signal.
摘要翻译：用于一个或多个载波信号的数字前端信道化装置包括每载波部分和复合部分。复合部分可以包括信号处理单元，每个信号处理单元可以包括用于将复合载波信号变换为时域信号的逆傅立叶变换单元，用于检测和选择时域信号的峰值的采样检测和选择单元，剪辑单元，用于剪辑时域复合载波信号以产生误差信号;傅立叶变换单元，用于将误差信号变换为频域误差信号;频率整形单元，用于对频域误差信号进行频率整形;求和单元，用于从复合载波信号减去频率形状的频域误差信号;以及相位选择单元，用于对所得到的信号进行相位调整。

38. 发明授权

US09477579B2 Embedded software debug system with partial hardware acceleration 有权
标题翻译：嵌入式软件调试系统，部分硬件加速
公开(公告)号：US09477579B2
公开(公告)日：2016-10-25
申请号：US13963256
申请日：2013-08-09
申请人： Kenneth E. Cecka , James T. Woodward
发明人： Kenneth E. Cecka , James T. Woodward
IPC分类号： G06F11/36
CPC分类号： G06F11/3656
摘要： An embedded software debug system with partial hardware acceleration includes a computer that executes a debug software stack. The debug software stack includes high level operations. The system also includes a remote microcontroller electronically connected to the computer. The system further includes an embedded processor electronically connected to the remote microcontroller. The remote microcontroller receives an applet from the computer and executes the applet in conjunction with the computer executing the debug software stack to debug the embedded processor. The applet includes low level protocol operations including performance critical tight-loops precompiled into machine code. The debug software stack may include a stub that replaces the tight-loops of the applet. The computer may send the applet to the remote microcontroller in response to executing the stub.
摘要翻译：具有部分硬件加速的嵌入式软件调试系统包括执行调试软件堆栈的计算机。调试软件栈包括高级操作。该系统还包括电子连接到计算机的远程微控制器。该系统还包括电子连接到远程微控制器的嵌入式处理器。远程微控制器从计算机接收小程序，并与执行调试软件堆栈的计算机一起执行小程序，以调试嵌入式处理器。该小程序包括低级协议操作，包括预编译到机器代码中的性能关键紧密循环。调试软件堆栈可以包括替代小程序的紧密循环的存根。响应于执行存根，计算机可以将小程序发送到远程微控制器。

39. 发明授权

US09477577B2 Method and apparatus for enabling an executed control flow path through computer program code to be determined 有权
标题翻译：能够确定通过计算机程序代码执行的控制流程路径的方法和装置
公开(公告)号：US09477577B2
公开(公告)日：2016-10-25
申请号：US14233401
申请日：2011-07-20
申请人： David Baca
发明人： David Baca
IPC分类号： G06F9/44 , G06F9/45 , G06F11/36 , G06F11/34
CPC分类号： G06F11/3624 , G06F11/3466 , G06F11/3612 , G06F11/3636 , G06F2201/865 , G06F2201/88
摘要： A method of enabling an executed control flow path through computer program code to be determined. The method comprising modelling cumulative instruction counts for control flow paths through the computer program code, and inserting at least one probe within the computer program code to enable a cumulative instruction count value for at least one control flow path of the computer program code to be accessed.
摘要翻译：能够确定通过计算机程序代码执行的控制流程的方法。该方法包括对通过计算机程序代码的控制流程路径的累积指令计数进行建模，以及在计算机程序代码内插入至少一个探针，以使得能够访问计算机程序代码的至少一个控制流程路径的累积指令计数值。

40. 发明授权

US09477548B2 Error repair location cache 有权
标题翻译：修复位置缓存时发生错误
公开(公告)号：US09477548B2
公开(公告)日：2016-10-25
申请号：US14450168
申请日：2014-08-01
申请人： Freescale Semiconductor Inc.
发明人： George P. Hoekstra , Ravindraraj Ramaraju
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F11/1064 , G06F11/1048
摘要： A method for repairing a memory includes executing an Error Correction Code (ECC) for a page of the memory. The page includes a plurality of bits having an inherent number of failed bits equal to or greater than zero. The ECC is configured to correct a correctable number of failed bits from the plurality of bits. A location of a failure prone bit in the page is determined from a cache in response to the correctable number of failed bits being less than the inherent number of failed bits. A state of the failure prone bit is changed to a new state in response to determining the location of the failure prone bit. The ECC is executed in response to the state of the failure prone bit being changed to the new state.
摘要翻译：一种用于修复存储器的方法包括对存储器的页面执行纠错码（ECC）。页面包括具有等于或大于零的故障比特的固有次数的多个比特。 ECC被配置为从多个比特校正可纠错数量的失败比特。响应于可修复数量的故障比特小于固有的失败比特数，从高速缓存确定页面中的故障倾向位的位置。响应于确定故障倾向位的位置，故障倾向位的状态变为新状态。响应于故障倾斜位的状态改变到新状态来执行ECC。

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