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31. 发明申请

US20230004329A1 MANAGED FETCHING AND EXECUTION OF COMMANDS FROM SUBMISSION QUEUES 有权
公开(公告)号：US20230004329A1
公开(公告)日：2023-01-05
申请号：US17940598
申请日：2022-09-08
申请人： SanDisk Technologies LLC
发明人： Shay Benisty
IPC分类号： G06F3/06
摘要： The disclosure relates in some aspects to managing the fetching and execution of commands stored in submission queues. For example, execution of a command may be blocked at a data storage apparatus due to an internal blocking condition (e.g., a large number of commands of a particular type are pending for execution at the data storage device). As another example, execution of a command may be blocked at a data storage apparatus due to an external blocking condition (e.g., a host device may specify that certain commands are to be executed immediately one after another). The disclosure relates in some aspects to controlling how commands are fetched and executed so that commands that cannot be executed by the data storage apparatus in the near future do not prevent other commands (that are not subject to the same blocking condition) from being executed.

32. 发明授权

US11545225B1 “Read after erase” method for catching single word line “slow to erase” signature in nonvolatile memory structures 有权
公开(公告)号：US11545225B1
公开(公告)日：2023-01-03
申请号：US17356823
申请日：2021-06-24
申请人： SanDisk Technologies LLC
发明人： Parth Amin , Anubhav Khandelwal
IPC分类号： G11C16/34 , G11C16/04 , G11C16/14 , G11C16/26 , G11C16/08 , G11C11/56
摘要： A method for detecting a “slow to erase” condition of a non-volatile memory structure, wherein the method comprises initiating an erase/verify memory operation with respect to the memory structure, wherein the erase/verify memory operation comprises applying an erase verify voltage according to an alternating word line scheme; following the erase/verify memory operation, determining if a first bit scan mode criteria is satisfied; and, if the first bit scan mode criteria is satisfied, initiating a read/verify memory operation wherein, the read/verify memory operation comprises applying a read-pass voltage according to an all word line scheme, and a magnitude of the read-pass voltage is greater than a magnitude of the erase verify voltage. Following the read/verify memory operation, the method also comprises determining if a second bit scan mode criteria is satisfied and, if the criteria is not satisfied, designating the memory structure with a fail status.

33. 发明授权

US11545221B2 Concurrent programming of multiple cells for non-volatile memory devices 有权
公开(公告)号：US11545221B2
公开(公告)日：2023-01-03
申请号：US17360572
申请日：2021-06-28
申请人： SanDisk Technologies LLC
发明人： Xiang Yang , Gerrit Jan Hemink , Ken Oowada , Toru Miwa
IPC分类号： G11C16/10 , G11C11/56 , G11C16/04 , G11C16/34 , G11C8/18 , G11C8/12
摘要： Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

34. 发明申请

US20220413036A1 VIRTUAL QUALITY CONTROL INTERPOLATION AND PROCESS FEEDBACK IN THE PRODUCTION OF MEMORY DEVICES 有权
公开(公告)号：US20220413036A1
公开(公告)日：2022-12-29
申请号：US17360573
申请日：2021-06-28
申请人： SanDisk Technologies LLC
发明人： Yusuke Ikawa , Tsuyoshi Sendoda , Kei Samura , Masaaki Higashitani
IPC分类号： G01R31/27 , G01R31/3183 , G01R31/317 , G01R31/3181 , G06N3/063
摘要： To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

35. 发明申请

US20220406387A1 Toggle Mode Frequency Optimization By Dynamic ODT Matching for Non-Volatile Memory 有权
公开(公告)号：US20220406387A1
公开(公告)日：2022-12-22
申请号：US17349965
申请日：2021-06-17
申请人： SANDISK TECHNOLOGIES LLC
发明人： Evgeny Vigdorchik , Nimrod Hermesh
IPC分类号： G11C16/32 , G11C16/04 , G11C16/26
摘要： A data storage system includes a plurality of memory dies and interface circuitry, including a receiver configured to receive pulses of a read clock signal; an I/O contact pad coupled to the receiver via a signal path of an interface channel; and on-die-termination (ODT) circuitry coupled to the I/O contact pad and the receiver. The ODT circuitry includes a plurality of resistor pairs, each including a pull-up resistor selectively coupled to the signal path via a first switch, and a pull-down resistor selectively coupled to the signal path via a second switch; and ODT control circuitry configured to enable ODT at the interface circuitry by causing each of the switches to be closed during a first stage of the read operation, and disable ODT at the interface circuitry by causing each of the switches to be open during a final stage of the read operation.

36. 发明申请

US20220406383A1 DIGITAL TEMPERATURE COMPENSATION FILTERING 有权
公开(公告)号：US20220406383A1
公开(公告)日：2022-12-22
申请号：US17352095
申请日：2021-06-18
申请人： SanDisk Technologies LLC
发明人： Henry Chin , Hua-Ling Cynthia Hsu , Wei Zhao , Fanglin Zhang
IPC分类号： G11C16/14 , G11C16/26 , G11C16/34 , G06F1/20
摘要： Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function. The smoothing function determines the temperature compensation value by selecting either the historical temperature value or the current temperature value as the temperature compensation value based on a difference between the historical temperature value and the current temperature relative to a threshold, or calculating the temperature compensation value, different from the current temperature value or the historical temperature value, based a smoothing function which utilizes the current temperature value and the historical temperature value.

37. 发明申请

US20220406380A1 WORD LINE ZONED ADAPTIVE INITIAL PROGRAM VOLTAGE FOR NON-VOLATILE MEMORY 有权
公开(公告)号：US20220406380A1
公开(公告)日：2022-12-22
申请号：US17351533
申请日：2021-06-18
申请人： SanDisk Technologies LLC
发明人： Erika Penzo , Han-Ping Chen , Henry Chin
IPC分类号： G11C16/08 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34
摘要： An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.

38. 发明申请

US20220406378A1 SYSTEMS AND METHODS FOR ADJUSTING THRESHOLD VOLTAGE DISTRIBUTION DUE TO SEMI-CIRCLE SGD 有权
公开(公告)号：US20220406378A1
公开(公告)日：2022-12-22
申请号：US17350770
申请日：2021-06-17
申请人： SanDisk Technologies LLC
发明人： Xiang Yang , Kazuki Isozumi , Parth Amin
IPC分类号： G11C16/04 , G11C16/10 , G11C16/26 , G11C16/34
摘要： The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.

39. 发明申请

US20220406342A1 Sense Amplifier Mapping and Control Scheme for Non-Volatile Memory 有权
公开(公告)号：US20220406342A1
公开(公告)日：2022-12-22
申请号：US17354613
申请日：2021-06-22
申请人： SANDISK TECHNOLOGIES LLC
发明人： Feng Lu , Jongyeon Kim , Ohwon Kwon
IPC分类号： G11C7/06 , G11C7/10
摘要： A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.

40. 发明申请

US20220404989A1 PROGRAMMING MEMORY CELLS WITH CONCURRENT REDUNDANT STORAGE OF DATA FOR POWER LOSS PROTECTION 有权
公开(公告)号：US20220404989A1
公开(公告)日：2022-12-22
申请号：US17349306
申请日：2021-06-16
申请人： SanDisk Technologies LLC
发明人： Xiang Yang , Toru Miwa , Ken Oowada , Gerrit Jan Hemink
IPC分类号： G06F3/06
摘要： Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

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