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31. 发明授权

US10241795B2 Guest to native block address mappings and management of native code storage 有权
公开(公告)号：US10241795B2
公开(公告)日：2019-03-26
申请号：US15208404
申请日：2016-07-12
申请人： Intel Corporation
发明人： Mohammad Abdallah
IPC分类号： G06F9/355 , G06F12/1036 , G06F9/455 , G06F9/30 , G06F9/32 , G06F9/38 , G06F12/0895 , G06F12/0897
摘要： A method for managing mappings of storage on a code cache for a processor. The method includes storing a plurality of guest address to native address mappings as entries in a conversion look aside buffer, wherein the entries indicate guest addresses that have corresponding converted native addresses stored within a code cache memory, and receiving a subsequent request for a guest address at the conversion look aside buffer. The conversion look aside buffer is indexed to determine whether there exists an entry that corresponds to the index, wherein the index comprises a tag and an offset that is used to identify the entry that corresponds to the index. Upon a hit on the tag, the corresponding entry is accessed to retrieve a pointer to the code cache memory corresponding block of converted native instructions. The corresponding block of converted native instructions are fetched from the code cache memory for execution.

32. 发明申请

US20190026232A1 HARDWARE-ASSISTED GUEST ADDRESS SPACE SCANNING IN A VIRTUALIZED COMPUTING SYSTEM 审中-公开
公开(公告)号：US20190026232A1
公开(公告)日：2019-01-24
申请号：US15655182
申请日：2017-07-20
申请人： VMware, Inc.
发明人： Andrei WARKENTIN , Alexander FAINKICHEN , Cyprien LAPLACE , Ye LI , Regis DUCHESNE
IPC分类号： G06F12/1036 , H04L12/801 , H04L12/755 , H04L12/24
摘要： An example method of scanning a guest virtual address (GVA) space generated by a guest operating system executing in a virtual machine of a virtualized computing system includes setting, in a scan of the GVA space by a hypervisor that manages the virtual machine, a current GVA to a first GVA in the GVA space; executing, on a processor allocated to the virtual machine, an address translation instruction, which is in an instruction set of the processor, to perform a first address translation of the current GVA; reading a register of the processor to determine a first error resulting from the first address translation; determining, in response to the first error, a level of a faulting page table in a first page table hierarchy generated by the guest operating system; and setting the current GVA to a second GVA based on the level of the faulting page table.

33. 发明申请

US20190018789A1 MEMORY ADDRESS TRANSLATION 审中-公开
公开(公告)号：US20190018789A1
公开(公告)日：2019-01-17
申请号：US15650056
申请日：2017-07-14
申请人： ARM LTD
发明人： Jonathan Curtis BEARD , Roxana RUSITORU , Curtis Glenn DUNHAM
IPC分类号： G06F12/1027 , G06F11/07 , G06F9/32 , G06F9/34 , G06F12/1036 , G06F9/38
摘要： Memory address translation apparatus comprises a translation data store to store one or more instances of translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicating a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space; detector circuitry to detect whether a given virtual memory address to be translated lies in the range of virtual memory addresses defined by an instance of the translation data in the translation data store; in which the detector circuitry is configured, when the given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, to retrieve one or more further instances of the translation data; and translation circuitry to apply the translation defined by a detected instance of the translation data to the given virtual memory address.

34. 发明授权

US10169246B2 Reducing metadata size in compressed memory systems of processor-based systems 有权
公开(公告)号：US10169246B2
公开(公告)日：2019-01-01
申请号：US15592611
申请日：2017-05-11
申请人： QUALCOMM Incorporated
发明人： Richard Senior , Christopher Edward Koob , Gurvinder Singh Chhabra , Andres Alejandro Oportus Valenzuela , Nieyan Geng , Raghuveer Raghavendra , Christopher Porter , Anand Janakiraman
IPC分类号： G06F3/06 , G06F12/02 , G06F12/1036
摘要： Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2N compressed data regions, corresponding 2N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2N compressed data regions and one of the 2N sets of free memory lists based on a modulus of the virtual address and 2N. The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.

35. 发明授权

US10169091B2 Efficient memory virtualization in multi-threaded processing units 有权
公开(公告)号：US10169091B2
公开(公告)日：2019-01-01
申请号：US13660799
申请日：2012-10-25
申请人： NVIDIA Corporation
发明人： Nick Barrow-Williams , Brian Fahs , Jerome F. Duluk, Jr. , James Leroy Deming , Timothy John Purcell , Lucien Dunning , Mark Hairgrove
IPC分类号： G06F9/46 , G06F15/173 , G06F9/50 , G06F12/1045 , G06F9/48 , G06F9/455 , G06F12/109 , G06F12/1036
摘要： A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

36. 发明申请

US20180373644A1 MULTI-PLANE MEMORY MANAGEMENT 审中-公开
公开(公告)号：US20180373644A1
公开(公告)日：2018-12-27
申请号：US15633388
申请日：2017-06-26
申请人： Western Digital Technologies, Inc.
发明人： Daniel Joseph Linnen , Ashish Ghai , Dongxiang Liao , Srikar Peesari , Avinash Rajagiri , Philip Reusswig , Bin Wu
IPC分类号： G06F12/1036 , G06F3/06 , G06F11/10 , G06F11/14 , G06F12/10
摘要： Apparatuses, systems, methods, and computer program products are disclosed for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.

37. 发明授权

US10162745B2 System and method of transfer of control between memory locations 有权
公开(公告)号：US10162745B2
公开(公告)日：2018-12-25
申请号：US15234431
申请日：2016-08-11
申请人： AO Kaspersky Lab
发明人： Vladislav V. Pintiysky , Denis V. Anikin , Dmitry A. Kirsanov
IPC分类号： G06F9/50 , G06F12/02 , G06F12/08 , G06F9/455 , G06F12/1009 , G06F12/1036
摘要： Disclosed are system and method for controlling execution of a program. An example method includes determining a memory sector for storing at least a portion of execution instructions of the computer program in virtual memory address space; determining, in the virtual memory address space, one or more pages that contain code instructions and data associated with the memory sector; creating a duplicate of the virtual memory address space comprising the memory sector and the one or more pages; tagging the memory sector and the one or more pages in both the virtual memory address space and its duplicate; receiving a notification to transfer execution of the computer program between different memory sectors while executing instructions stored in either the virtual memory address space or its duplicate; and transferring execution of the computer program to a memory location other than the one in which the notification was received.

38. 发明授权

US10162659B2 Embedded processor with virtualized security controls using guest identifications, a common kernel address space and operational permissions 有权
公开(公告)号：US10162659B2
公开(公告)日：2018-12-25
申请号：US14953909
申请日：2015-11-30
申请人： ARM Finance Overseas Limited
发明人： Sanjay Patel , Ranjit Joseph Rozario
IPC分类号： G06F12/10 , G06F12/14 , G06F9/455 , G06F12/1036 , G06F12/109
摘要： A method includes assigning unique guest identifications to different guests, specifying an address region and permissions for the different guests and controlling a guest jump from one physical memory segment to a second physical memory segment through operational permissions defined in a root memory management unit that supports guest isolation and protection.

39. 发明申请

US20180336140A1 METHOD AND SYSTEM FOR FLASH-AWARE HEAP MEMORY MANAGEMENT 审中-公开
公开(公告)号：US20180336140A1
公开(公告)日：2018-11-22
申请号：US15981402
申请日：2018-05-16
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： VISHAK GUDDEKOPPA , ARUN GEORGE , MUTHA SANJAY MITESH , RAKESH NADIG
IPC分类号： G06F12/1036 , G06F12/1009 , G06F12/02 , G06F12/126
摘要： A method for flash-aware heap memory management includes reserving a contiguous virtual space in a memory space of at least one process with a size equivalent to a size of a flash-based byte addressable device. The method also includes partitioning by a host device the memory space of the flash-based byte addressable device into multiple chunks. Each chunk includes multiple logical segments. The host device receives a memory allocation request from a thread associated with an application. The host device determines at least one chunk from the multiple chunks, including a least free logical segment compared to the other chunks from the multiple chunks. The host device allocates to the thread at least one chunk that includes the least free logical segment.

40. 发明授权

US10120813B2 Address translation 有权
公开(公告)号：US10120813B2
公开(公告)日：2018-11-06
申请号：US15452989
申请日：2017-03-08
申请人： ARM Limited
发明人： John Michael Horley , Dan Brook
IPC分类号： G06F12/1009 , G06F12/1036
摘要： Address translation apparatus comprises translation circuitry to access an ordered set of two or more address translation tables stored at respective storage locations to generate an address translation between an input virtual memory address in a virtual memory address space and a respective translated memory address in a translated memory address space. Each address translation table in the ordered set of two or more address translation tables is configured to provide translation data indicating mappings between virtual memory addresses and translated memory addresses for a contiguous range of virtual memory addresses applicable to that address translation table. The ordered set of address translation tables are ordered with respect to one another according to an order of their respective ranges of virtual memory addresses for which they provide translation data. Each address translation table in the ordered set of two or more address translation tables comprises location information defining the storage location of at least those of the other address translation tables in the ordered set of two or more address translation tables which are adjacent to that address translation table in the ordered set of two or more address translation tables.

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