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31. 发明授权

US07508937B2 Programmable data encryption engine for advanced encryption standard algorithm 有权
标题翻译：可编程数据加密引擎，用于高级加密标准算法
公开(公告)号：US07508937B2
公开(公告)日：2009-03-24
申请号：US10255971
申请日：2002-09-26
申请人： Yosef Stein , Haim Primo
发明人： Yosef Stein , Haim Primo
IPC分类号： H04K1/04
CPC分类号： H04L9/0631 , H04L2209/125
摘要： A programmable data encryption engine for performing the cipher function of an advanced encryption standard (AES) algorithm includes a parallel look-up table system responsive in a first mode to a first data block for implementing an AES selection function and executing the multiplicative inverse in GF−1(28) and applying an affine over GF(2) transformation to obtain a subbyte transformation and in a second mode to the subbyte transformation to transform the subbyte transformation to obtain a shift row transformation, and a Galois field multiplier for transforming the shift row transformation to obtain a mix column transformation and add a round key resulting in an advanced encryption standard cipher function of the first data block.
摘要翻译：用于执行高级加密标准（AES）算法的加密功能的可编程数据加密引擎包括：以第一模式响应于第一数据块的并行查找表系统，用于实现AES选择功能并在GF中执行乘法逆 -1（28），并且在GF（2）变换上应用仿射以获得子字节变换，并且在第二模式中对子字节变换进行变换以变换子字节变换以获得移位行变换;以及用于变换移位的伽罗瓦域乘法器行转换以获得混合列转换并添加一个循环密钥，产生第一数据块的高级加密标准密码函数。

32. 发明申请

US20090060202A1 Ternary and Higher Multi-Value Digital Scramblers/Descramblers 审中-公开
标题翻译：三元和更高的多值数字加扰器/解扰器
公开(公告)号：US20090060202A1
公开(公告)日：2009-03-05
申请号：US12264728
申请日：2008-11-04
申请人： Peter Lablans
发明人： Peter Lablans
IPC分类号： H04K1/04
CPC分类号： H04L25/03866
摘要： Ternary (3-value) and higher, multi-value digital scramblers/descramblers in digital communications. The method and apparatus of the present invention includes the creation of ternary (3-value) and higher value truth tables that establish ternary and higher value scrambling functions which are its own descrambling functions. The invention directly codes by scrambling ternary and higher-value digital signals and directly decodes by descrambling with the same function. A disclosed application of the invention is the creation of composite ternary and higher-value scrambling devices and methods consisting of single scrambling devices or functions combined with ternary or higher value shift registers. Another disclosed application is the creation of ternary and higher-value spread spectrum digital signals. Another disclosed application is a composite ternary or higher value scrambling system, comprising an odd number of scrambling functions and the ability to be its own descrambler.
摘要翻译：三值（3值）以上，多值数字加扰/解码器在数字通信。本发明的方法和装置包括创建三值（3值）和更高价值的真值表，其建立作为它自己的解扰功能的三值和更高值的加扰函数。本发明通过对三进制数值信号进行加扰直接编码，并通过相同功能的解扰直接解码。本发明的公开的应用是创建由单个扰码设备或与三元或更高值移位寄存器组合的功能组成的复合三元和更高值的加扰设备和方法。另一个公开的应用是创建三值和更高价值的扩频数字信号。另一个公开的应用是复合三元或更高值的加扰系统，其包括奇数个加扰功能以及作为其自己的解扰器的能力。

33. 发明授权

US07492894B2 Information-processing apparatus, control method, program and recording medium 失效
标题翻译：信息处理装置，控制方法，程序和记录介质
公开(公告)号：US07492894B2
公开(公告)日：2009-02-17
申请号：US10979708
申请日：2004-11-02
申请人： Satoshi Kitani , Tomoyuki Asano
发明人： Satoshi Kitani , Tomoyuki Asano
IPC分类号： H04K1/04 , G06F15/18
CPC分类号： H04L9/0662 , H04L9/0637 , H04L9/0844 , H04L9/3242
摘要： A 4-byte LBA (logical block address) specified in a read command is supplied to first and second IV (initialization vector) generation units. The initialization-vector generation units each extend the LBA to data with a size of 16 bytes by applying typically a hash function to the LBA. The first initialization-vector generation unit outputs the data with a size of 16 bytes to an encryption unit as an initialization vector IV. On the other hand, the second initialization-vector generation unit outputs the data with a size of 16 bytes to a decryption unit as an initialization vector IV. The encryption unit encrypts input data by using the initialization vector IV and a session key Ks received from a first authentication-processing unit. On the other hand, the decryption unit decrypts input data by using the initialization vector IV and the session key Ks received from a second authentication-processing unit.
摘要翻译：在读命令中指定的4字节LBA（逻辑块地址）被提供给第一和第二IV（初始化向量）生成单元。初始化向量生成单元通过将典型的哈希函数应用于LBA，将LBA扩展为具有16字节大小的数据。第一初始化向量生成单元将具有16字节大小的数据作为初始化向量IV输出到加密单元。另一方面，第二初始化向量生成单元将具有16字节大小的数据作为初始化向量IV输出到解密单元。加密单元通过使用从第一认证处理单元接收到的初始化向量IV和会话密钥Ks来加密输入数据。另一方面，解密单元通过使用从第二认证处理单元接收到的初始化向量IV和会话密钥Ks来解密输入数据。

34. 发明申请

US20080130891A1 INTEGRATED CIRCUIT DEVICE INTERFACE WITH PARALLEL SCRAMBLER AND DESCRAMBLER 审中-公开
标题翻译：集成电路设备接口与并行SCRAMBLER和DESCRAMBLER
公开(公告)号：US20080130891A1
公开(公告)日：2008-06-05
申请号：US11935303
申请日：2007-11-05
申请人： Alvin Sun , Steven Pan , Frank Lin
发明人： Alvin Sun , Steven Pan , Frank Lin
IPC分类号： H04K1/04
CPC分类号： H04L9/0656 , H04L2209/125
摘要： An interface for an integrated circuit (IC) device. The interface includes a scrambler to combine a plurality of plaintext data streams and a pseudorandom key sequence. The scrambler includes a pseudorandom number (PRN) source and a combiner. The PRN source provides a pseudorandom number. The pseudorandom key sequence is based on the pseudorandom number. The combiner receives the plurality of plaintext data streams in parallel and output a corresponding plurality of ciphertext data streams in parallel to another IC device interface. The interface also may include a descrambler to separate a pseudorandom key sequence out of a plurality of parallel ciphertext data streams. By scrambling plaintext data streams and descrambling ciphertext data streams in parallel, the data transmission rate on the IC device may be slower than a data transmission rate used to transfer data between IC devices.
摘要翻译：一种用于集成电路（IC）器件的接口。该接口包括用于组合多个明文数据流和伪随机密钥序列的加扰器。加扰器包括伪随机数（PRN）源和组合器。 PRN源提供伪随机数。伪随机密钥序列基于伪随机数。组合器并行地接收多个明文数据流，并且与另一个IC设备接口并行地输出相应的多个密文数据流。接口还可以包括解扰器，以从多个并行密文数据流中分离伪随机密钥序列。通过对明文数据流进行加扰并并行解密密文数据流，IC器件上的数据传输速率可能比用于在IC器件之间传输数据的数据传输速率慢。

35. 发明授权

US07352861B2 Digital electronic component which is protected against electrical-type analyses 有权
标题翻译：防止电气分析的数字电子部件
公开(公告)号：US07352861B2
公开(公告)日：2008-04-01
申请号：US10498605
申请日：2002-12-11
申请人： Jean-Luc Dauvois , Jérôme Perrine
发明人： Jean-Luc Dauvois , Jérôme Perrine
IPC分类号： H04K1/04 , H04K1/06 , H04K1/00 , H04L9/00 , H04L9/32 , G06F11/30 , G06F12/14 , G06K19/06 , G06K5/00 , G06F17/00
CPC分类号： G06K19/0723 , G06K7/0008
摘要： This invention relates to a digital electronic component which is protected against electrical- and/or electromagnetic-type analyse). The inventive component comprises: a synchronous element (10) which is controlled by a clock (H); means (11, 12) of generating said clock (H), the frequency of which varies randomly between a minimum value and a maximum value for at least a given period of time; and means (13) of controlling the random nature of the frequency change of said clock (H).
摘要翻译：本发明涉及一种数字电子部件，该数字电子部件可防止电气和/或电磁型分析）。本发明的部件包括：由时钟（H）控制的同步元件（10）; 产生所述时钟（H）的装置（11,12），其频率在至少给定时间段内在最小值和最大值之间随机变化; 以及控制所述时钟（H）的频率变化的随机特性的装置（13）。

36. 发明申请

US20070286418A1 SIMPLE UNIVERSAL HASH FOR PLAINTEXT AWARE ENCRYPTION 有权
标题翻译：简单的通用加密软件
公开(公告)号：US20070286418A1
公开(公告)日：2007-12-13
申请号：US11843783
申请日：2007-08-23
申请人： William Hall , Charanjit Jutla
发明人： William Hall , Charanjit Jutla
IPC分类号： H04K1/04
CPC分类号： H04L9/0643
摘要： A simple universal hash apparatus and method include input means for inputting at least one of a plurality of Plaintext blocks into an integrity aware encryption scheme using at least one of two secret keys to obtain a plurality of Ciphertext blocks; Plaintext checksum means for computing a Plaintext checksum value from said plurality of Plaintext blocks; Ciphertext checksum means for processing said plurality of Ciphertext blocks and a third key to obtain a Ciphertext checksum; and combination means for combining said Plaintext checksum and said Ciphertext checksum to obtain the simple universal hash value.
摘要翻译：一种简单的通用散列装置和方法包括输入装置，用于使用两个秘密密钥中的至少一个将多个明文块中的至少一个输入到完整性感知加密方案中以获得多个密文块; 明文校验和是指用于从所述多个明文块计算明文校验和值的装置; 用于处理所述多个密文块的加密文本校验和装置和第三密钥以获得密文校验和; 以及用于组合所述明文校验和和所述密文校验和以获得简单的通用散列值的组合装置。

37. 发明申请

US20070237327A1 Method and System for High Throughput Blockwise Independent Encryption/Decryption 有权
标题翻译：高吞吐量的独立加密/解密方法和系统
公开(公告)号：US20070237327A1
公开(公告)日：2007-10-11
申请号：US11690034
申请日：2007-03-22
申请人： David Taylor , Ronald Indeck , Jason White , Roger Chamberlain
发明人： David Taylor , Ronald Indeck , Jason White , Roger Chamberlain
IPC分类号： H04L9/28 , H04K1/06 , H04L9/00 , H04K1/04 , H04K1/00
CPC分类号： H04L9/0637 , H04L9/0662 , H04L9/14 , H04L2209/125 , H04L2209/24
摘要： An encryption technique is disclosed for encrypting a data segment comprising a plurality of data blocks, wherein the security and throughput of the encryption is enhanced by using blockwise independent bit vectors for reversible combination with the data blocks prior to key encryption. Preferably, the blockwise independent bit vectors are derived from a data tag associated with the data segment. Several embodiments are disclosed for generating these blockwise independent bit vectors. In a preferred embodiment, the data tag comprises a logical block address (LBA) for the data segment. Also disclosed herein is a corresponding decryption technique as well as a corresponding symmetrical encryption/decryption technique.
摘要翻译：公开了一种用于加密包括多个数据块的数据段的加密技术，其中通过在密钥加密之前使用与数据块可逆组合的块独立比特向量来增强加密的安全性和吞吐量。优选地，从与数据段相关联的数据标签导出块独立比特向量。公开了用于产生这些块独立比特向量的几个实施例。在优选实施例中，数据标签包括用于数据段的逻辑块地址（LBA）。这里也公开了相应的解密技术以及对应的对称加密/解密技术。

38. 发明申请

US20070230690A1 System for write failure recovery 审中-公开
标题翻译：写入失败恢复系统
公开(公告)号：US20070230690A1
公开(公告)日：2007-10-04
申请号：US11397101
申请日：2006-04-03
申请人： Reuven Elhamias , Vivek Mani , Niv Cohen
发明人： Reuven Elhamias , Vivek Mani , Niv Cohen
IPC分类号： H04K1/06 , H04K1/04
CPC分类号： H04L9/0637 , H04L9/0894
摘要： When cipher block chaining encryption/decryption is employed, write fault recovery is accomplished by storing information useful for the writing of cipher block chaining processed data before it is written to storage cells. Hence when write failure is discovered, this information stored can be retrieved for rewriting the data to the cells. Preferably, the information stored includes security configuration information for cipher block chaining processing a unit of data.
摘要翻译：当采用密码块链接加密/解密时，通过在将密码块链接处理的数据写入存储单元之前存储有用的写入信息来实现写入故障恢复。因此，当发现写入失败时，可以检索存储的信息以将数据重写到单元。优选地，存储的信息包括用于密码块链接处理数据单元的安全配置信息。

39. 发明授权

US07263186B2 Speed-up hardware architecture for CCMP encryption protocol 有权
标题翻译：加速硬件架构，用于CCMP加密协议
公开(公告)号：US07263186B2
公开(公告)日：2007-08-28
申请号：US10721289
申请日：2003-11-26
申请人： Chih-Pen Chang , Ming-Shiang Lai
发明人： Chih-Pen Chang , Ming-Shiang Lai
IPC分类号： H04K1/04
CPC分类号： H04L9/0631 , H04L2209/125 , H04L2209/80
摘要： A speed-up hardware architecture used in wireless encryption/decryption operation comprises: a plurality of operation units, that each operation unit is capable of accomplishing a designated operation independently, further comprising: a data receiving device having two inputs that a first input is used for receiving an external data signal and a second input is used for receiving a supporting signal coming from the other operation unit, wherein when an operating mode of the data receiving device is “normal”, the data receiving device will output the first input, and when an operating mode of the data receiving device is “speed-up”, the data receiving device will output the second input; and an operating device coupling to the data receiving device for processing the data from the data receiving device and outputting the processed data thereafter; and a control unit coupling to every operation unit in the architecture for enabling the operation units which are idle to assist the working operation units for data processing, further comprising: a controlling device coupling to the data receiving device of every operation unit in the architecture for issuing a control signal and changing operating mode; and an integrating device coupling to the operating device of every operation unit in the architecture for integrating outputs coming from the operating devices of operation units which are in “speed-up mode”.
摘要翻译：在无线加密/解密操作中使用的加速硬件架构包括：多个操作单元，每个操作单元能够独立地完成指定操作，还包括：数据接收装置，具有使用第一输入的两个输入用于接收外部数据信号，第二输入用于接收来自其他操作单元的支持信号，其中当数据接收设备的操作模式为“正常”时，数据接收设备将输出第一输入，并且当数据接收装置的操作模式为“加速”时，数据接收装置将输出第二输入; 以及耦合到所述数据接收装置的操作装置，用于处理来自所述数据接收装置的数据，并且此后输出所述经处理的数据; 以及控制单元，其耦合到所述架构中的每个操作单元，用于使所述空闲的操作单元能够辅助所述工作操作单元进行数据处理，还包括：控制设备，其耦合到所述架构中的每个操作单元的数据接收装置，发出控制信号并改变运行模式; 以及集成装置，其耦合到该结构中的每个操作单元的操作装置，用于对来自处于“加速模式”的操作单元的操作装置的输出进行积分。

40. 发明申请

US20070195952A1 Method And System For Computational Transformation 有权
标题翻译：计算转型方法与系统
公开(公告)号：US20070195952A1
公开(公告)日：2007-08-23
申请号：US11572635
申请日：2004-09-14
申请人： Prahlad Singanamala
发明人： Prahlad Singanamala
IPC分类号： H04L9/28 , H04K1/06 , H04L9/00 , H04K1/04 , H04K1/00
CPC分类号： H04L9/0618 , H04L9/0643 , H04L9/0662 , H04L2209/24
摘要： The invention generally relates to computational transformation process, which has applications in cryptography, random number generation, hash code generation etc. The computational transformation module uses a keyset, which is designed using a two dimensional array. Since the process of forward transformation used in the invention is a symmetric encryption process and if used to send data securely over a communications network, the same keyset needs to be present at the sending computer to encrypt the data and the receiving computer to go through a reverse transformation and decrypt the data. When the first ‘n’ bit block of input-data is transformed into the first ‘m’ bit block of output-data, the keyset is transformed into a different keyset based on a nonlinear or one-way transformation on the keyset. The next input block is encrypted using a transformed keyset, hence satisfying Shanons theory of perfect secrecy. It uses the same logic with additional parameters and operations to create random numbers and unique hash codes. The computational transformation process is a one-way process which is based on a principle where given the input value ‘x’, it is easy to transform ‘x’ to ‘y’ using a function ‘F’ i.e. F(x)=y. However, given ‘y’ in the range of F, it is hard to find an x such that F(x)=y. In this system, the same transformation function and same keyset is used for both encryption as well as decryption with only a change in the constant value.
摘要翻译：本发明一般涉及计算变换过程，其具有密码学，随机数生成，散列码生成等的应用。计算变换模块使用使用二维数组设计的密钥集。由于本发明中使用的正向转换过程是对称加密过程，并且如果用于通过通信网络安全地发送数据，则需要在发送计算机上存在相同的密钥集以加密数据和接收计算机以通过逆向转换和解密数据。当输入数据的第一个'n'比特块被转换成输出数据的第一个'm'比特块时，基于键集上的非线性或单向变换将密钥集转换成不同的密钥集。下一个输入块使用转换的密钥集进行加密，从而满足Shanons完美保密的理论。它使用与附加参数和操作相同的逻辑来创建随机数和唯一的哈希码。计算变换过程是基于给定输入值“x”的原理的单向过程，使用函数“F”很容易将“x”转换为“y”，即F（x）= y 。然而，给定'F'范围内的'y'，很难找到一个x，使得F（x）= y。在该系统中，相同的转换函数和相同的密钥集用于加密和解密，只有常数值的变化。

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