专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US09136132B2 Manganese metal film forming method, processing system, electronic device manufacturing method and electronic device 有权
标题翻译：锰金属成膜方法，加工系统，电子器件制造方法和电子器件
公开(公告)号：US09136132B2
公开(公告)日：2015-09-15
申请号：US14140889
申请日：2013-12-26
申请人： TOKYO ELECTRON LIMITED
发明人： Kenji Matsumoto , Peng Chang
IPC分类号： H01L21/20 , H01L21/36 , H01L21/285 , H01L23/532 , H01L21/67 , H01L21/768 , C23C16/18 , C23C16/40
CPC分类号： H01L21/28556 , C23C16/18 , C23C16/40 , H01L21/67207 , H01L21/76814 , H01L21/76828 , H01L21/76831 , H01L21/76846 , H01L21/76855 , H01L21/76867 , H01L21/76882 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A manganese metal film forming method includes: degassing an underlying layer formed on a processing target by thermally treating the processing target, the underlying layer containing silicon and oxygen; and forming a manganese metal film on the degassed underlying layer by chemical deposition using a gas containing a manganese compound. Forming a manganese metal film includes introducing a gas containing an oxidizing agent to form a partially-oxidized manganese metal film.
摘要翻译：锰金属膜形成方法包括：通过热处理处理目标，含有硅和氧的下层，对形成在处理目标上的下层进行脱气; 以及通过使用含有锰化合物的气体进行化学沉积在脱气的下层上形成锰金属膜。形成锰金属膜包括引入含氧化剂的气体以形成部分氧化的锰金属膜。

32. 发明授权

US09117907B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09117907B2
公开(公告)日：2015-08-25
申请号：US14607613
申请日：2015-01-28
申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.
发明人： Zhongshan Hong
IPC分类号： H01L27/12 , H01L29/78 , H01L21/36 , H01L29/06 , H01L29/10 , H01L29/16 , H01L29/161 , H01L29/20 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L29/785 , H01L29/0649 , H01L29/1033 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/495 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66795 , H01L29/78
摘要： A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer.
摘要翻译：公开了半导体器件的制造工艺。该方法包括提供半导体衬底，其具有形成在半导体衬底上的第一绝缘层和形成在第一绝缘层的表面上的鳍，以及在鳍的侧壁上形成完全耗尽的半导体层，以及完全耗尽的半导体层具有不同于翅片的材料。该方法还包括形成覆盖完全耗尽的半导体层的第二绝缘层，以及去除鳍以形成暴露完全耗尽的半导体层的侧壁的开口。此外，该方法包括在完全耗尽的半导体层的侧壁的一部分上形成栅极电介质层，使得全部耗尽的半导体层的侧壁的一部分形成半导体器件的沟道区，并且形成栅电极层覆盖栅介电层。

33. 发明授权

US09099611B2 Light emitting device 有权
标题翻译：发光装置
公开(公告)号：US09099611B2
公开(公告)日：2015-08-04
申请号：US13735607
申请日：2013-01-07
申请人： LG INNOTEK CO., LTD.
发明人： Yong Tae Moon
IPC分类号： H01L31/00 , H01L31/0256 , H01L21/36 , H01L21/20 , H01L33/32 , H01L21/02 , H01L33/00 , H01L33/12 , H01L33/44
CPC分类号： H01L33/32 , H01L21/0242 , H01L21/02458 , H01L21/02488 , H01L21/02502 , H01L21/02538 , H01L21/0254 , H01L33/007 , H01L33/12 , H01L33/44 , H01L2224/48091 , H01L2924/00014
摘要： Disclosed is a method for fabricating a light emitting device. The method includes forming an oxide including gallium aluminum over a gallium oxide substrate, forming a nitride including gallium aluminum over the oxide including gallium aluminum and forming a light emitting structure over the nitride including gallium aluminum.
摘要翻译：公开了一种制造发光器件的方法。该方法包括在氧化镓衬底上形成包括镓铝的氧化物，在包括镓铝的氧化物上形成包括镓铝的氮化物，并在包括镓铝的氮化物上形成发光结构。

34. 发明授权

US09093384B2 Substrate, semiconductor device, and method of manufacturing the same 有权
公开(公告)号：US09093384B2
公开(公告)日：2015-07-28
申请号：US14495336
申请日：2014-09-24
申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.
发明人： Keiji Ishibashi
IPC分类号： H01L21/20 , H01L21/36 , H01L31/0312 , H01L21/304 , H01L21/02 , H01L29/16 , C30B29/36 , C30B33/00 , H01L21/28 , H01L29/34 , H01L29/36 , H01L29/45 , H01L29/49 , H01L29/66 , H01L29/78 , H01L29/04
CPC分类号： H01L21/304 , C30B23/025 , C30B29/36 , C30B33/00 , H01L21/02002 , H01L21/02008 , H01L21/0201 , H01L21/02378 , H01L21/0243 , H01L21/02433 , H01L21/02529 , H01L21/02658 , H01L21/28 , H01L29/045 , H01L29/1608 , H01L29/167 , H01L29/34 , H01L29/36 , H01L29/45 , H01L29/4966 , H01L29/66068 , H01L29/7802 , H01L29/7813 , Y10T428/21
摘要： A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation σ of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation σ of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.

35. 发明授权

US09087691B2 Method for manufacturing graphene nano-ribbon, mosfet and method for manufacturing the same 有权
标题翻译：石墨烯纳米带的制造方法，其制造方法及其制造方法
公开(公告)号：US09087691B2
公开(公告)日：2015-07-21
申请号：US13510390
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/20 , H01L21/36 , H01L21/02 , H01L29/775 , H01L29/06 , H01L29/16 , H01L29/20 , H01L29/66 , H01L29/786 , B82Y10/00 , B82Y40/00 , B82Y30/00
CPC分类号： H01L21/0242 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/02422 , H01L21/02488 , H01L21/02491 , H01L21/02507 , H01L21/02527 , H01L21/02639 , H01L29/0673 , H01L29/1606 , H01L29/2003 , H01L29/66742 , H01L29/775 , H01L29/78684 , H01L29/78696
摘要： A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.
摘要翻译：提供了具有石墨烯纳米带的MOSFET及其制造方法。 MOSFET包括绝缘基板; 和绝缘基板上的氧化物保护层。至少一个石墨烯纳米带被嵌入在氧化物保护层中并且具有暴露在氧化物保护层的侧表面的表面。在所述至少一个石墨烯纳米带的每个中设置有沟道区。在所述至少一个石墨烯纳米带的每一个中设置源极区和漏极区。沟道区位于源区和漏区之间。栅电介质位于至少一个石墨烯纳米带上。栅极电介质上的栅极导体。源极和漏极触点分别在氧化物保护层的侧表面上接触源极区域和漏极区域。

36. 发明授权

US09082615B2 Polysilicon manufacturing method that controls growth direction of polysilicon 有权
标题翻译：控制多晶硅生长方向的多晶硅制造方法
公开(公告)号：US09082615B2
公开(公告)日：2015-07-14
申请号：US14235764
申请日：2013-11-18
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Xiang Zhang
IPC分类号： H01L21/36 , H01L21/02
CPC分类号： H01L21/02532 , H01L21/02488 , H01L21/02494 , H01L21/02502 , H01L21/02595 , H01L21/02636 , H01L21/02675
摘要： The present invention provides a polysilicon manufacturing method that controls a growth direction of polysilicon, including the following steps: (1) forming a first buffer layer (20) on a substrate (10) through deposition; (2) applying a masking operation to form a lens-like structure (22) on a surface of the first buffer layer (20); (3) depositing and forming an amorphous silicon layer (40) on the first buffer layer (20) of which the surface comprises the lens-like structure (22) formed thereon; (4) subjecting the amorphous silicon layer (40) to rinsing; (5) irradiating the amorphous silicon layer (40) with an intense light (50) from the side of the substrate (10) so as to generate a crystal seed at a bottom of the amorphous silicon layer (40); and (6) applying a laser annealing operation to the amorphous silicon layer (40) that comprises a crystal seed generated therein so as to have amorphous silicon contained in the amorphous silicon layer (40) crystallized and forming a polysilicon layer (70). The present invention enables control of the growth direction of polysilicon.
摘要翻译：本发明提供一种控制多晶硅生长方向的多晶硅制造方法，包括以下步骤：（1）通过沉积在基板（10）上形成第一缓冲层（20）; （2）在第一缓冲层（20）的表面上施加掩模操作以形成透镜状结构（22）; （3）在其上形成有透镜状结构（22）的第一缓冲层（20）上沉积和形成非晶硅层（40）（4）对非晶硅层（40）进行漂洗; （5）从所述基板（10）的一侧用强光（50）照射所述非晶硅层（40），以在所述非晶硅层（40）的底部产生晶种; 和（6）对包含在其中产生的晶种的非晶硅层（40）施加激光退火操作，以使非晶硅层（40）中包含的非晶硅结晶并形成多晶硅层（70）。本发明能够控制多晶硅的生长方向。

37. 发明授权

US09040392B2 Method for controlled removal of a semiconductor device layer from a base substrate 有权
公开(公告)号：US09040392B2
公开(公告)日：2015-05-26
申请号：US13161260
申请日：2011-06-15
申请人： Stephen W. Bedell , Cheng-Wei Cheng , Devendra K. Sadana , Kuen-Ting Shiu , Norma E. Sosa Cortes
发明人： Stephen W. Bedell , Cheng-Wei Cheng , Devendra K. Sadana , Kuen-Ting Shiu , Norma E. Sosa Cortes
IPC分类号： H01L21/36 , H01L21/18 , H01L21/78 , H01L21/02 , H01L31/18
CPC分类号： H01L21/187 , H01L21/02002 , H01L21/7813 , H01L31/1892 , Y02E10/50
摘要： A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.

38. 发明授权

US09023733B2 Method for block-copolymer lithography 有权
标题翻译：嵌段共聚物光刻法
公开(公告)号：US09023733B2
公开(公告)日：2015-05-05
申请号：US14038565
申请日：2013-09-26
申请人： IMEC , Tokyo Electron Limited
发明人： Boon Teik Chan , Shigeru Tahara
IPC分类号： H01L21/302 , H01L21/461 , H01L21/4763 , H01L21/20 , H01L21/36 , H01L21/027 , B81C1/00 , H01L21/033 , H01L21/311
CPC分类号： H01L21/0271 , B81C1/00031 , G03F7/0002 , H01L21/0337 , H01L21/31138
摘要： The present disclosure relates to a method (10) for block-copolymer lithography. This method comprises the step of obtaining (12) a self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, and the steps of applying at least once each of first plasma etching (14) of said self-organizing block-copolymer layer using a plasma formed from a substantially ashing gas, and second plasma etching (16) of said self-organizing block-copolymer layer using plasma formed from a pure inert gas or mixture of inert gases in order to selectively remove a first polymer phase. A corresponding intermediate product also is described.
摘要翻译：本发明涉及一种嵌段共聚物光刻法（10）。该方法包括获得（12）包含至少两个具有相互不同的抗蚀性的聚合物组分的自组织嵌段共聚物层的步骤，以及施加至少一次所述自组装嵌段共聚物的第一等离子体蚀刻（14）使用由基本灰分气体形成的等离子体组织嵌段共聚物层，以及使用由纯惰性气体或惰性气体混合物形成的等离子体进行第二等离子体蚀刻（16）所述自组织嵌段共聚物层，以选择性地除去第一聚合物相。还描述了相应的中间产物。

39. 发明授权

US09012277B2 In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices 有权
标题翻译：在PMOS和NMOS器件中嵌入的应力区域的原位掺杂和无扩散退火
公开(公告)号：US09012277B2
公开(公告)日：2015-04-21
申请号：US13346043
申请日：2012-01-09
申请人： Stefan Flachowsky , Ralf Illgen
发明人： Stefan Flachowsky , Ralf Illgen
IPC分类号： H01L21/70 , H01L21/8238 , H01L21/36 , H01L21/268 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L21/823807 , H01L21/268 , H01L21/2686 , H01L21/823814 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and substantially diffusionless annealing techniques. One illustrative method disclosed herein includes forming first and second cavities in PMOS and NMOS device regions, respectively, of a semiconductor substrate, and thereafter performing first and second epitaxial deposition processes to form in situ doped first and second embedded material regions in the first and second cavities, respectively. The method further includes, among other things, performing a single heat treating process to activate dopants in the in situ doped first and second embedded material regions.
摘要翻译：通常，本公开涉及使用原位掺杂和基本上无扩散退火技术在诸如晶体管元件等的半导体器件中形成双嵌入应力源区域的方法。本文公开的一种说明性方法包括分别在半导体衬底的PMOS和NMOS器件区域中形成第一和第二空腔，然后执行第一和第二外延沉积工艺，以在第一和第二外延材料区域中形成第一和第二外延材料区域腔。该方法还包括执行单一热处理工艺以激活原位掺杂的第一和第二嵌入材料区域中的掺杂剂。

40. 发明授权

US08969130B2 Insulating film, formation method thereof, semiconductor device, and manufacturing method thereof 有权
标题翻译：绝缘膜，其形成方法，半导体器件及其制造方法
公开(公告)号：US08969130B2
公开(公告)日：2015-03-03
申请号：US13675140
申请日：2012-11-13
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tetsuhiro Tanaka , Erika Takahashi , Yuki Imoto , Yuhei Sato
IPC分类号： H01L21/00 , H01L29/786 , H01L21/36 , H01L29/66 , H01L21/02
CPC分类号： H01L29/7869 , H01L21/02189 , H01L21/02194 , H01L21/02266 , H01L29/66742 , H01L29/66969 , H01L29/78603 , Y10T428/24628
摘要： An amorphous region with low density is formed in an oxide insulating film containing zirconium. The amount of oxygen released from such an oxide insulating film containing zirconium by heating is large and a temperature at which oxygen is released is higher in the oxide insulating film than in a conventional oxide film (e.g., a silicon oxide film). When the insulating film is formed using a sputtering target containing zirconium in an oxygen atmosphere, the temperature of a surface on which the insulating film is formed may be controlled to be lower than a temperature at which a film to be formed starts to crystallize.
摘要翻译：在含锆的氧化物绝缘膜中形成低密度的非晶区域。通过加热从含氧锆的氧化物绝缘膜释放出的氧量比氧化物绝缘膜（例如，氧化硅膜）的氧化物绝缘膜的释放温度高。当在氧气氛中使用含有锆的溅射靶形成绝缘膜时，可以将形成有绝缘膜的表面的温度控制为低于待形成的膜开始结晶的温度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式