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31. 发明授权

US07595262B2 Manufacturing method for an integrated semiconductor structure 有权
标题翻译：集成半导体结构的制造方法
公开(公告)号：US07595262B2
公开(公告)日：2009-09-29
申请号：US11588591
申请日：2006-10-27
申请人： Till Schlösser
发明人： Till Schlösser
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/8236 , H01L21/8234 , H01L21/8242 , H01L21/336 , H01L21/44 , H01L21/28
CPC分类号： H01L27/10894 , H01L27/10882 , H01L27/10891
摘要： A manufacturing method for an integrated semiconductor structure and a corresponding semiconductor structure is disclosed. The method includes forming a peripheral circuitry in a peripheral device region, wherein the peripheral circuitry includes a peripheral transistor at least partially formed in the semiconductor substrate and having a first gate dielectric formed in a first high temperature process step. The method further includes forming a plurality of memory cells in a memory cell region, each of said memory cells including an access transistor at least partially formed in a semiconductor substrate and having a second gate dielectric formed in a second high temperature process step and having a metallic gate conductor. The first and second high temperature process steps are performed before a step of forming the metallic gate conductor.
摘要翻译：公开了一种用于集成半导体结构和相应的半导体结构的制造方法。该方法包括在外围设备区域中形成外围电路，其中外围电路包括至少部分地形成在半导体衬底中并具有在第一高温工艺步骤中形成的第一栅极电介质的外围晶体管。该方法还包括在存储器单元区域中形成多个存储单元，每个存储单元包括至少部分地形成在半导体衬底中并具有在第二高温工艺步骤中形成的第二栅电介质的存取晶体管，金属栅极导体。第一和第二高温工艺步骤在形成金属栅极导体的步骤之前进行。

32. 发明授权

US07588987B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07588987B2
公开(公告)日：2009-09-15
申请号：US11319572
申请日：2005-12-29
申请人： Ji Hwan Yu
发明人： Ji Hwan Yu
IPC分类号： H01L21/8236 , H01L31/062
CPC分类号： H01L21/265 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device and a method for fabricating the same selectively forms a nitride layer having high tensile stress in an NMOS transistor area, to thereby form a strained-silicon structure in an NMOS channel region, whereby electron mobility is improved and drain current is increased. The semiconductor device includes an isolation region that, electrically isolates an N-type MOS transistor area from a P-type MOS transistor area, and a nitrade layer formed on an entire upper surface of a substrate, wherein the nitrade layer has silicon ions (Si+) selectively implanted in the P-type MOS transistor area.
摘要翻译：半导体器件及其制造方法在NMOS晶体管区域中选择性地形成具有高拉伸应力的氮化物层，从而在NMOS沟道区域中形成应变硅结构，从而提高电子迁移率并且增加漏极电流。半导体器件包括：将N型MOS晶体管区域与P型MOS晶体管区域电隔离的隔离区域和形成在衬底整个上表面上的氮化层，其中氮化层具有硅离子（Si + ）选择性地植入P型MOS晶体管区域。

33. 发明申请

US20090189202A1 ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE HAVING PORTIONS WITH DIFFERENT CONDUCTIVITY TYPES AND A PROCESS OF FORMING THE SAME 有权
标题翻译：包括具有不同导电类型的部分的门电极的电子装置及其形成方法
公开(公告)号：US20090189202A1
公开(公告)日：2009-07-30
申请号：US12020316
申请日：2008-01-25
申请人： Burchell B. Baptiste
发明人： Burchell B. Baptiste
IPC分类号： H01L29/00 , H01L21/8236
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/792
摘要： An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type.
摘要翻译：电子器件可以包括具有不同导电类型的不同部分的栅电极。在一个实施例中，形成电子器件的工艺可以包括在衬底上形成半导体层，其中半导体层具有特定的导电类型。该工艺还可以包括选择性地掺杂半导体层的区域以形成具有相反导电类型的第一掺杂区域。该工艺可以进一步包括图案化半导体层以形成包括第一部分和第二部分的栅电极，其中第一部分包括第一掺杂区域的一部分，第二区域包括部分半导体层第一掺杂区域。在特定实施例中，电子设备可以具有栅电极，其具有一个导电类型的边缘部分和具有相反导电类型的中心部分。

34. 发明申请

US20090146223A1 PROCESS AND METHOD TO LOWER CONTACT RESISTANCE 审中-公开
标题翻译：降低接触电阻的方法和方法
公开(公告)号：US20090146223A1
公开(公告)日：2009-06-11
申请号：US11950574
申请日：2007-12-05
申请人： Sameer H. Jain , Shreesh Narasimha , Karen A. Nummy , Katsunori Onishi , Viorel C. Ontalus , Jang H. Sim
发明人： Sameer H. Jain , Shreesh Narasimha , Karen A. Nummy , Katsunori Onishi , Viorel C. Ontalus , Jang H. Sim
IPC分类号： H01L29/94 , H01L21/8236
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/268 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/808 , H01L29/812
摘要： A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method then performs a laser anneal on the additional impurity (to activate the additional impurity) or amorphized regions (to recrystallize the amorphized regions). After this, permanent spacers are formed on the sidewalls of the gate conductor. Then, the surface regions of the substrate not protected by the gate conductor and the permanent spacers are silicided, to create silicide source/drain regions. This forms the silicide regions in the additional impurity or in the recrystallized amorphized regions to reduce the source/drain resistance by improving the active dopant concentration at the silicon-silicide interface.
摘要翻译：一种方法从晶体管栅极堆叠的侧面去除间隔物，并且在间隔物被去除之后，该方法将不附加栅极导体保护的衬底的另外的杂质注入到衬底的表面区域中（或者只是将这些表面区域非晶化，而不添加更多的杂质）。然后，该方法对另外的杂质（以激活附加杂质）或非晶化区域（使非晶化区域重结晶）进行激光退火。之后，在栅极导体的侧壁上形成永久的间隔物。然后，将不被栅极导体和永久性间隔物保护的衬底的表面区域硅化，以产生硅化物源极/漏极区域。这会在附加杂质或再结晶非晶化区域中形成硅化物区域，以通过改善硅硅化物界面处的活性掺杂剂浓度来降低源/漏电阻。

35. 发明授权

US07534676B2 Method of forming enhanced device via transverse stress 有权
标题翻译：通过横向应力形成增强器件的方法
公开(公告)号：US07534676B2
公开(公告)日：2009-05-19
申请号：US11828961
申请日：2007-07-26
申请人： Robert C. Bowen , Yuguo Wang
发明人： Robert C. Bowen , Yuguo Wang
IPC分类号： H01L21/8236
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regions has a direction through the channel region. Dielectric regions create a compressive stress on the channel region perpendicular to the current flow.
摘要翻译：在本发明中，PMOS器件包括在{100}硅中形成的沟道区，其中第一和第二源/漏区设置在沟道区的任一侧上。沟道区域被定向成使得源极/漏极区域之间的电流流过通道区域的<100>方向。电介质区域在与电流垂直的沟道区域上产生压缩应力。

36. 发明申请

US20090014812A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090014812A1
公开(公告)日：2009-01-15
申请号：US12168427
申请日：2008-07-07
申请人： Junli Wang , Tomoyuki Hirano , Toyotaka Kataoka , Yoshiya Hagimoto
发明人： Junli Wang , Tomoyuki Hirano , Toyotaka Kataoka , Yoshiya Hagimoto
IPC分类号： H01L21/8236 , H01L27/088
CPC分类号： H01L21/82385 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L21/823835 , H01L21/823857 , H01L21/823871 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein is a semiconductor device, including: a first group of transistors formed on a semiconductor substrate; and a second group of transistors formed on the semiconductor substrate, each of which is lower in operating voltage than each of the transistors in the first group; wherein each of the transistors in the first group includes a first gate electrode formed on the semiconductor substrate through a first gate insulating film, and a silicide layer formed on the first gate electrode; each of the transistors in the second group includes a second gate electrode formed in a trench for gate formation, formed in an insulating film above the semiconductor substrate, through a second gate insulating film; and a protective film is formed so as to cover the silicide layer on each of the first gate electrodes of the first group of transistors.
摘要翻译：本文公开了一种半导体器件，包括：形成在半导体衬底上的第一组晶体管; 以及形成在所述半导体基板上的第二组晶体管，每个晶体管的工作电压低于所述第一组中的每个晶体管; 其中第一组中的每个晶体管包括通过第一栅极绝缘膜形成在半导体衬底上的第一栅电极和形成在第一栅电极上的硅化物层; 第二组中的每个晶体管包括形成在用于栅极形成的沟槽中的第二栅电极，其通过第二栅极绝缘膜形成在半导体衬底上方的绝缘膜中; 并且形成保护膜以覆盖第一晶体管组的每个第一栅电极上的硅化物层。

37. 发明申请

US20080283923A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080283923A1
公开(公告)日：2008-11-20
申请号：US12025057
申请日：2008-02-04
申请人： Chen-Yueh Li , Yi-Wei Chen , Ming-Yan Chen
发明人： Chen-Yueh Li , Yi-Wei Chen , Ming-Yan Chen
IPC分类号： H01L29/00 , H01L21/8236
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1251 , H01L29/78621
摘要： A semiconductor device and a manufacturing method thereof are provided. The manufacturing method can form a structure of a thin film transistor (TFT) having a symmetric lightly doped region, and thus provide superior operation reliability and electrical performance. In addition, the manufacturing method forms gate patterns of different TFTs by the same mask process and thereby avoids the misalignment of masks so as to improve the processing yield and reduce the manufacturing cost.
摘要翻译：提供了一种半导体器件及其制造方法。该制造方法可以形成具有对称的轻掺杂区域的薄膜晶体管（TFT）的结构，从而提供优异的操作可靠性和电性能。此外，制造方法通过相同的掩模工艺形成不同TFT的栅极图案，从而避免掩模的未对准，从而提高加工成品率并降低制造成本。

38. 发明申请

US20080182075A1 Phosphorus Containing Si Epitaxial Layers in N-Type Source/Drain Junctions 有权
标题翻译：含N型源极/漏极的Si外延层的磷
公开(公告)号：US20080182075A1
公开(公告)日：2008-07-31
申请号：US11957820
申请日：2007-12-17
申请人： Saurabh Chopra , Zhiyuan Ye , Yihwan Kim
发明人： Saurabh Chopra , Zhiyuan Ye , Yihwan Kim
IPC分类号： H01L21/8236 , H01L21/20 , C04B41/50 , B32B3/00
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/66628 , H01L29/7834 , Y10T428/24612
摘要： Methods for formation of epitaxial layers containing n-doped silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the n-doped epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source, a carbon source and an n-dopant source. An epitaxial layer may have considerable tensile stress which may be created in a significant amount by a high concentration of n-dopant. A layer having n-dopant may also have substitutional carbon. Phosphorus as an n-dopant with a high concentration is provided. A substrate having an epitaxial layer with a high level of n-dopant is also disclosed.
摘要翻译：公开了形成含有n掺杂硅的外延层的方法。具体实施例涉及半导体器件中的外延层的形成和处理，例如金属氧化物半导体场效应晶体管（MOSFET）器件。在具体实施方案中，n掺杂外延层的形成包括将处理室中的衬底暴露于包括硅源，碳源和n-掺杂剂源的沉积气体。外延层可能具有相当大的拉伸应力，这可以通过高浓度的n-掺杂物以显着的量产生。具有n-掺杂剂的层也可以具有取代的碳。提供了作为高浓度的n掺杂剂的磷。还公开了具有高水平的n掺杂剂的外延层的衬底。

39. 发明申请

US20080169531A1 METHODS OF FORMING NANO LINE STRUCTURES IN MICROELECTRONIC DEVICES AND RELATED DEVICES 失效
标题翻译：在微电子器件中形成纳米线结构的方法及相关器件
公开(公告)号：US20080169531A1
公开(公告)日：2008-07-17
申请号：US11853313
申请日：2007-09-11
申请人： ZongLiang Huo , Subramanya Mayya , Xiaofeng Wang , In-Seok Yeo
发明人： ZongLiang Huo , Subramanya Mayya , Xiaofeng Wang , In-Seok Yeo
IPC分类号： H01L29/24 , H01L21/8236
CPC分类号： H01L51/0049 , B82Y10/00 , H01L29/0665 , H01L29/0673
摘要： A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermined length greater than the width. At least one nano line is formed in the nano line arrangement region extending substantially along the length thereof and coupled to the surface of the groove structure to define a nano line structure. Related devices are also discussed.
摘要翻译：形成微电子器件的方法包括在衬底上形成具有相对侧壁及其表面的沟槽结构，以限定纳米线布置区域。纳米线排列区域具有预定宽度和大于宽度的预定长度。在纳米线布置区域中形成至少一条纳米线，其基本上沿着其长度延伸并耦合到凹槽结构的表面以限定纳米线结构。还讨论了相关设备。

40. 发明授权

US07396727B2 Transistor of semiconductor device and method for fabricating the same 有权
标题翻译：半导体器件的晶体管及其制造方法
公开(公告)号：US07396727B2
公开(公告)日：2008-07-08
申请号：US11615812
申请日：2006-12-22
申请人： Jeong-Ho Park
发明人： Jeong-Ho Park
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8236
CPC分类号： H01L29/66666 , H01L21/26586 , H01L29/105 , H01L29/7827
摘要： A transistor which may effectively control the short channel effect with a vertical transistor structure. This structure may prevent the degradation of a transistor's performance caused by the hot carrier effect. The transistor has a source region having a concentration of implanted impurity ions on a semiconductor substrate; a channel region having a cylindrical shape over the source region; a drain region formed over the channel region; a gate insulation layer formed over the source region, a side of the channel region, and the drain region; and a gate conductor extending over an upper portion and one side of the channel region.
摘要翻译：可以用垂直晶体管结构有效地控制短沟道效应的晶体管。这种结构可以防止由热载流子效应引起的晶体管性能的劣化。晶体管具有在半导体衬底上具有注入的杂质离子浓度的源区; 在所述源极区域上具有圆柱形状的沟道区域; 漏极区，形成在所述沟道区上; 形成在源极区域，沟道区域侧和漏极区域上的栅极绝缘层; 以及在沟道区域的上部和一侧延伸的栅极导体。

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