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    • 37. 发明授权
    • Multiplexing and demultiplexing data
    • 复用和解复用数据
    • US08902748B2
    • 2014-12-02
    • US14089229
    • 2013-11-25
    • Adrian Ioan NistorJason Pelly
    • Adrian Ioan NistorJason Pelly
    • H04J1/16H04J3/02H04J3/04
    • H04J3/02H04J3/047
    • Apparatus arranged to perform data multiplexing or demultiplexing or a non-transitory computer readable medium comprising a computer program which, when executed by a computer, carries out a method of multiplexing or demultiplexing data, the apparatus comprising a memory, an interface, and a processing unit arranged to determine locations of corresponding regions of the memory for corresponding channels based on data sizes and time-unit-numbers that have passed since a previous corresponding quantity of channel data for a corresponding channel was last stored in the memory or processed, wherein the data sizes and time-unit numbers correspond to one or more channels of the plurality of channels, such that the processing unit will not store the corresponding quantity of the channel data, for each corresponding channel of the plurality of channels, at a location in the memory that is currently storing any channel data that has not yet been output or processed.
    • 被布置为执行数据复用或解复用的装置或包括计算机程序的非暂时性计算机可读介质,所述计算机程序当由计算机执行时执行复用或解复用数据的方法,所述装置包括存储器,接口和处理 单元,被配置为基于从相应频道的先前相应数量的频道数据最后存储在所述存储器中或经处理而已经通过的数据大小和时间单位数,确定用于相应频道的存储器的对应区域的位置,其中, 数据大小和时间单元号对应于多个信道中的一个或多个信道,使得处理单元将不存储针对多个信道中的每个相应信道的相应数量的信道数据 正在存储任何尚未被输出或处理的通道数据的存储器。
    • 38. 发明授权
    • Fault tolerant parallel receiver interface with receiver redundancy
    • 具有接收机冗余的容错并行接收器接口
    • US08861513B2
    • 2014-10-14
    • US13736353
    • 2013-01-08
    • International Business Machines Corporation
    • Timothy O. DicksonDaniel M. DrepsFrank D. Ferraiolo
    • H04L12/50H04L12/28H04L12/66H04J3/02H04L27/00H04L12/24G06F13/00H04L12/933
    • H04L41/00G06F11/2007G06F13/00H04L49/10
    • A communications parallel bus receiver interface having N+1 data lines and method of operation. The parallel bus interface employs receiver redundancy at the bus level such that there are N+1 receiver devices. One of the N+1 data signals comprising a spare data signal when a failure occurs in a corresponding channel transmitting one of N parallel data signals. An input switching network is configured to receive and couple N+1 parallel data signals along respective paths to corresponding parallel-configured bit receiver devices, and adapted to couple one received data signal to two or three adjacent bit receivers. A calibration device calibrates one of the two or three adjacent bit receivers, and a qualification device qualifies data decisions made during calibration processes performed by the calibration device. The method cycles through N+1 receivers for periodic recalibration of each receiver (one at a time) while N+1 inputs are processed continuously and uninterrupted.
    • 具有N + 1条数据线和操作方法的通信并行总线接收器接口。 并行总线接口在总线电平上采用接收机冗余,使得存在N + 1个接收机设备。 在发送N个并行数据信号中的一个的相应信道中发生故障时,N + 1个数据信号中的一个包括备用数据信号。 输入交换网络被配置为沿着相应的路径接收并耦合N + 1个并行数据信号到相应的并行配置的位接收器设备,并且适于将一个接收的数据信号耦合到两个或三个相邻的位接收器。 校准装置校准两个或三个相邻位接收器中的一个,并且鉴定装置限定由校准装置执行的校准过程期间进行的数据决定。 该方法通过N + 1个接收机周期性地重新校准每个接收机(一次一个),而N + 1个输入被连续不间断地处理。