专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US09871649B2 Real time subsample time resolution signal alignment in time domain 有权
公开(公告)号：US09871649B2
公开(公告)日：2018-01-16
申请号：US15194800
申请日：2016-06-28
申请人： NATIONAL INSTRUMENTS CORPORATION
发明人： Aditya Chopra , Sean P. Ferguson
IPC分类号： H04L7/02 , H04L7/00 , G06F13/28 , G06F9/44
CPC分类号： H04L7/02 , G06F9/44 , G06F13/28 , G06F17/5022 , G06F17/5031 , G06F17/5054 , G06F2217/84 , H04L7/0029 , H04L7/0033 , H04L7/0041
摘要： System and method for subsample time resolution signal alignment. First and second signals may be aligned by iteratively performing the following until a termination condition is met: current samples of the first and second signals may be acquired, a delayed copy of the current samples of the first signal may be generated and subtracted from the current samples of the first signal to generate a third signal, a delayed copy of the current samples of the second signal may be generated with a current subsample delay and subtracted from the current samples of the first signal to generate a fourth signal, and an alignment error may be generated based on the third and fourth signals and the current subsample may be delay adjusted accordingly. The iteratively adjusting may generate a subsample resolution delay aligning the second signal to the first signal. Subsequent samples the first signal and the second signal may be aligned and output per the subsample resolution delay.

32. 发明申请

US20170303147A1 METHODS AND APPARATUSES FOR ADVANCED RECEIVER DESIGN 审中-公开
公开(公告)号：US20170303147A1
公开(公告)日：2017-10-19
申请号：US15630444
申请日：2017-06-22
申请人： InterDigital Technology Corporation
发明人： Allan Y. Tsai , William E. Lawton , Lakshmi R. Iyer , Muhammad U. Fazili , Manasa Raghavan
IPC分类号： H04W24/02 , H04W56/00 , H04L5/00 , H04B17/336 , H04L27/34 , H04L27/26 , H04L7/02 , H04W52/12
CPC分类号： H04W24/02 , H04B17/336 , H04L5/005 , H04L7/02 , H04L27/265 , H04L27/3494 , H04M2207/206 , H04W28/0236 , H04W52/12 , H04W56/0035
摘要： Disclosed are embodiments of apparatuses and methods of use thereof for frequency domain (FD) chip level (CL) equalizers used in wireless receivers. The FD-CL-EQ may further selectively apply a higher order matrix inverse or a lower order matrix inverse in the calculation of a channel estimate based on whether interference is present or not. Further disclosed are embodiments of methods and apparatuses for estimating pilot signal-to-interference ratio (SIR) in the wireless receivers. Further disclosed are methods and apparatuses for compensating for phase errors in received demodulated data symbols to improve performance of the wireless receivers.

33. 发明申请

US20170272233A1 METHOD AND APPARATUS FOR GENERATING STANDARD PATTERN FOR DATA SIGNALS 审中-公开
公开(公告)号：US20170272233A1
公开(公告)日：2017-09-21
申请号：US15460367
申请日：2017-03-16
申请人： SAMSUNG SDS CO., LTD.
发明人： In Suk PARK , Sang Joon SUN , Seung Jun LEE , Dae Jung AHN
IPC分类号： H04L7/02 , H04L7/00
CPC分类号： H04L7/02 , H04L7/0041 , H04L7/041 , H04Q9/00
摘要： Methods and apparatus for generating a standard pattern for data signals from a set of multiple data signals are provided. The standard pattern consists of a signal length, a centerline, an upper limit, and a lower limit. One of methods comprises, receiving first and second data signals, determining a standard pattern length for each of the first and second data signals, sampling each of the first and second data signals by as much as the determined standard pattern length, aligning the sampled first and second data signals, and generating a standard pattern for the first and second data signals by overlapping the aligned first and second data signals, wherein the generated standard pattern is a standard pattern having reflected thereinto upper and lower limit ranges that are determined using levels of the aligned first and second data signals.

34. 发明授权

US09769514B2 Clock recovery for video encoding/transcoding applications 有权
公开(公告)号：US09769514B2
公开(公告)日：2017-09-19
申请号：US14697145
申请日：2015-04-27
申请人： Harmonic, Inc.
发明人： Shahab Hamidi-Rad
IPC分类号： H04L7/02 , H04N21/43
CPC分类号： H04N21/4305
摘要： Approaches for clock synchronization in digital video environments. In an embodiment, an encoder/transcoder calculates a ratio between a system clock and a source clock. The source clock is used by a source device to encode or transcode digital video. The system clock is used by the encoder/transcoder. After the encoder/transcoder receives the digital video from the source device, the encoder/transcoder uses the calculated ratio to create a recovered clock. The recovered clock is locked to a frequency of the source clock but not to the phase of the source clock. The encoder/transcoder uses the recovered clock to encode or transfer the digital video received from the source device. The encoder/transcoder ensures that the frequency of the recovered clock does not change faster than a certain rate, e.g., 0.075 Hz/second.

35. 发明授权

US09762382B1 Time-aligning a signal 有权
公开(公告)号：US09762382B1
公开(公告)日：2017-09-12
申请号：US15046686
申请日：2016-02-18
申请人： Teradyne, Inc.
发明人： Lawrence B. Luce
IPC分类号： H04L7/02
CPC分类号： H04L7/02 , H03G3/3042 , H04B2001/0416 , H04L27/0002
摘要： An example method includes: obtaining sinusoidal signals comprising components of a first time-domain signal; shifting phases of the sinusoidal signals by amounts corresponding to a specified time-shift to produce phase-shifted signals, and converting the phase-shifted signals to the time domain to produce time-shifted signals. The shifting may be performed to more closely align an envelope of the first time-domain signal with an envelope of a second time-domain signal.

36. 发明申请

US20170251155A1 SWITCH CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS, AND MAGNETIC INK READING APPARATUS 有权
公开(公告)号：US20170251155A1
公开(公告)日：2017-08-31
申请号：US15503179
申请日：2014-09-29
申请人： Mitsubishi Electric Corporation
发明人： Akio KAMIMURAI , Takayuki NAKAI
IPC分类号： H04N5/369 , H02M7/5387 , H04L7/02 , H02M7/48 , H04N3/14 , H04N5/335
CPC分类号： H04N5/369 , G06K9/186 , G11C19/28 , H02M7/48 , H02M7/5387 , H02M2001/0054 , H04L7/02 , H04N3/14 , H04N5/335 , H04N5/3742 , H04N5/378
摘要： A first flip-flop outputs a first output signal as a first switch signal that controls a first switch. A second flip-flop outputs a second output signal based on a clock signal and the first output signal. A first inverting circuit generates a first inverted signal obtained by inverting the first output signal. A second AND circuit outputs a signal that is an AND of the first inverted signal and the second output signal, as a second switch signal that controls a second switch.

37. 发明申请

US20170244542A1 TIME-ALIGNING A SIGNAL 有权
公开(公告)号：US20170244542A1
公开(公告)日：2017-08-24
申请号：US15046686
申请日：2016-02-18
申请人： Teradyne, Inc.
发明人： Lawrence B. Luce
IPC分类号： H04L7/02
CPC分类号： H04L7/02 , H03G3/3042 , H04B2001/0416 , H04L27/0002
摘要： An example method includes: obtaining sinusoidal signals comprising components of a first time-domain signal; shifting phases of the sinusoidal signals by amounts corresponding to a specified time-shift to produce phase-shifted signals, and converting the phase-shifted signals to the time domain to produce time-shifted signals. The shifting may be performed to more closely align an envelope of the first time-domain signal with an envelope of a second time-domain signal.

38. 发明申请

US20170126332A1 ULTRASONIC COMMUNICATION SYSTEM 审中-公开
公开(公告)号：US20170126332A1
公开(公告)日：2017-05-04
申请号：US15039243
申请日：2014-11-26
申请人： Board of Trustees of Michigan State University
发明人： Subir BISWAS , Stephan LORENZ , Bo DONG , Qiong HUO
IPC分类号： H04B11/00 , H04W4/00 , H04W56/00 , H04L7/00 , H04L7/02
CPC分类号： H04B11/00 , G08B25/009 , H04L7/0037 , H04L7/02 , H04W4/38 , H04W4/70 , H04W56/0015
摘要： A sensor network includes a sink and multiple sensor nodes. The sink is coupled to a substrate and configured to transmit a periodic ultrasonic pulse on the substrate. A first one of the sensor nodes is coupled to the substrate. The first sensor node is configured to (i) receive the periodic ultrasonic pulse from the substrate, (ii) synchronize an internal clock of the first sensor node to the sink based on the periodic ultrasonic pulse, (iii) selectively detect an event in a region surrounding the first sensor node, and (iv) in response to detecting the event, transmit a first ultrasonic pulse toward the sink on the substrate.

39. 发明授权

US09621335B2 Interferometric precise timing distribution with a precision phase detector 有权
公开(公告)号：US09621335B2
公开(公告)日：2017-04-11
申请号：US14507105
申请日：2014-10-06
申请人： Honeywell International Inc.
发明人： David Paul Campagna
IPC分类号： G06F15/16 , H04L7/02 , H04J3/06 , H04L12/26 , G06F1/12 , H04B10/00 , G01C19/567 , H04L7/00
CPC分类号： H04L7/02 , H04J3/0682 , H04L7/0008 , H04L7/0033 , H04L43/08
摘要： A method distributing data in a network is provided. The method comprises measuring the path lengths between a reference clock and a plurality of remote destinations and sending a timing signal from the reference clock to the plurality of remote destinations. The method further comprises measuring the phase between the reference clock and a return signal from each of the plurality of remote destinations and adjusting the phase of the data such that each remote destination receives the data within a skew tolerance.

40. 发明授权

US09594396B2 Synchronizing data transfer between a first clock domain and second clock domain 有权
标题翻译：在第一个时钟域和第二个时钟域之间同步数据传输
公开(公告)号：US09594396B2
公开(公告)日：2017-03-14
申请号：US13703582
申请日：2011-07-26
申请人： Edward James Turner , Jon Beecroft
发明人： Edward James Turner , Jon Beecroft
IPC分类号： G06F1/12 , G06F5/12 , H04L7/02
CPC分类号： G06F1/12 , G06F5/12 , H04L7/02
摘要： A data processing system comprises a first clock domain having a first clock rate, a second clock domain having a second clock rate, and a data path operable to transfer data items from the first clock domain to the second clock domain. The data path comprises a buffer having an input for receiving data items from the first clock domain, and an output port for transmitting data items to the second clock domain in a first-in first-out manner. The buffer has a first pointer for indication of a current first location of the buffer, and a second pointer for indication of a current second location of the buffer. The system further includes a read controller operable to define a read pattern for the buffer, to control output from the buffer in dependence upon such a read pattern, and to adjust such a read pattern in dependence upon a value of such a first pointer for the buffer.
摘要翻译：数据处理系统包括具有第一时钟速率的第一时钟域，具有第二时钟速率的第二时钟域和可操作以将数据项从第一时钟域传送到第二时钟域的数据路径。数据路径包括具有用于从第一时钟域接收数据项的输入的缓冲器和用于以先进先出的方式将数据项发送到第二时钟域的输出端口。缓冲器具有用于指示缓冲器的当前第一位置的第一指针和用于指示缓冲器的当前第二位置的第二指示器。该系统还包括读取控制器，其可操作以定义缓冲器的读取模式，以依赖于这种读取模式来控制来自缓冲器的输出，并且根据这样的第一指针的值来调整这样的读取模式缓冲。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式