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41. 发明授权

US08865482B2 Method of detecting the circular uniformity of the semiconductor circular contact holes 有权
标题翻译：检测半导体圆形接触孔的圆形均匀性的方法
公开(公告)号：US08865482B2
公开(公告)日：2014-10-21
申请号：US14053750
申请日：2013-10-15
申请人： Shanghai Huali Microelectronics Corporation
发明人： Kai Wang , HungLin Chen , Yin Long , Qiliang Ni , MingShen Kuo
IPC分类号： H01L21/00 , H01L21/20 , H01L21/36 , H01L27/15 , H01L29/18 , H01L31/12 , H01L33/00 , H01L23/48 , H01L29/40 , H01L21/66
CPC分类号： H01L22/12 , H01L2924/0002 , Y10S257/911 , Y10S257/912 , H01L2924/00
摘要： A method of detecting the circular uniformity of semiconductor circular contact holes. Several detection circuit structures are disposed on the semiconductor wafer: N-type active regions and P-type active regions; silicon dioxide layers separate the N-type active regions from the P-type active regions; the N-type active regions are formed in the P well and the P-type active regions are formed in the N well; polysilicon gates bridge the N-type active regions and the P-type active regions; gate oxide layers insulate the P-type regions and the N-type regions from the polysilicon gates, so that the P-type regions and the N-type regions are independent; the N-type active regions connect with circular contact holes while the P-type active regions and the polysilicon gates connect with oval contact holes; a electron beam scanner detects the circular uniformity of the contact holes. This invention advantageously reflects effectively and comprehensively the circular uniformity of the contact holes.
摘要翻译：一种检测半导体圆形接触孔的圆形均匀性的方法。多个检测电路结构设置在半导体晶片上：N型有源区和P型有源区; 二氧化硅层将N型有源区与P型有源区分开; 在P阱中形成N型有源区，在N阱中形成P型有源区; 多晶硅门桥接N型有源区和P型有源区; 栅极氧化层使P型区域和N型区域与多晶硅栅极绝缘，使得P型区域和N型区域是独立的; N型有源区域与圆形接触孔连接，而P型有源区域和多晶硅栅极与椭圆形接触孔连接; 电子束扫描器检测接触孔的圆形均匀性。本发明有利地有效地反映了接触孔的圆形均匀性。

42. 发明申请

US20140302656A1 Method of Forming Ultra Shallow Junction 审中-公开
标题翻译：形成超浅结的方法
公开(公告)号：US20140302656A1
公开(公告)日：2014-10-09
申请号：US14091433
申请日：2013-11-27
申请人： Shanghai Huali Microelectronics Corporation
发明人： TianJin XIAO
IPC分类号： H01L21/265 , H01L29/66
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/2658 , H01L29/6659
摘要： The present invention discloses a method of forming ultra shallow junction, wherein the method includes the following steps: (1) providing a grid side wall etched semiconductor structure; (2) after the implantation of the nitrogen source ion into the said semiconductor structures, implanting the boron ions into the said structure of semiconductor by lightly doped drain (LDD) process; (3) forming an ultra shallow junction on the semiconductor structure by continuous processes of the heavily doped ions implantation and the anneal. The new source of N28 was introduced into this invention. N28 can reduce the diffusion of boron atom in the silicon substrate, and it can not interact with silicon atom to form the covalent bond. Hence, it overcomes problem of the aggravation of polysilicon gate depletion layer when carbon assisted ion implantation. Meanwhile, an ultra shallow junction is formed by simple process.
摘要翻译：本发明公开了一种形成超浅结的方法，其中该方法包括以下步骤：（1）提供栅格侧壁蚀刻的半导体结构; （2）在将氮源离子注入所述半导体结构之后，通过轻掺杂漏极（LDD）工艺将硼离子注入到所述半导体结构中; （3）通过重掺杂离子注入和退火的连续工艺在半导体结构上形成超浅结。 N28的新来源被引入本发明。 N28可以减少硅衬底中硼原子的扩散，并且它不能与硅原子相互作用形成共价键。因此，克服了碳辅助离子注入时多晶硅栅耗尽层恶化的问题。同时，通过简单的工艺形成超浅结。

43. 发明申请

US20140302254A1 PLASMA CLEANING METHOD 审中-公开
标题翻译：等离子体清洗方法
公开(公告)号：US20140302254A1
公开(公告)日：2014-10-09
申请号：US14081502
申请日：2013-11-15
申请人： Shanghai Huali Microelectronics Corporation
发明人： Ningbo Sang , Jun Zhou
IPC分类号： H01L21/02
CPC分类号： C23C16/4405 , B08B9/00
摘要： A plasma cleaning method is disclosed, the method includes the steps of performing a remote plasma cleaning; performing an in-situ radio-frequency nitrogen plasma cleaning; and depositing a seasoning film, wherein a reactant gas introduced in depositing the seasoning film does not include any nitrogen-containing gas. Advantageously, the combined use of the remote plasma cleaning and in-situ RF nitrogen plasma cleaning processes, as well as the non-use of any nitrogen-containing gas during the deposition of the seasoning film, can together greatly improve the conventional wafer backside metal contamination problem.
摘要翻译：公开了一种等离子体清洗方法，该方法包括进行远程等离子体清洗的步骤; 进行原位射频氮等离子体清洗; 并沉积调味膜，其中在沉积调味膜时引入的反应物气体不包括任何含氮气体。有利地，组合使用远程等离子体清洗和原位RF氮等离子体清洗工艺以及在调节膜沉积期间不使用任何含氮气体可以大大改善传统的晶片背面金属污染问题。

44. 发明申请

US20140273388A1 METHOD OF MANUFACTURING THE TRENCH OF U-SHAPE 有权
标题翻译：制造U形纹的方法
公开(公告)号：US20140273388A1
公开(公告)日：2014-09-18
申请号：US14070060
申请日：2013-11-01
申请人： Shanghai Huali Microelectronics Corporation
发明人： XuBin Jing , Fang Li , WenYan Liu
IPC分类号： H01L29/08 , H01L29/66
CPC分类号： H01L29/0847 , H01L21/47576 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/092 , H01L29/66477 , H01L29/66636 , H01L29/78
摘要： The present invention relates to the manufacture of CMOS semiconductor device. This invention includes: Step S1, a layer of silicon oxide is deposited covering the surface of the polysilicon gates and the exposed upper surface of the silicon substrate, the silicon oxide layer is removed on the upper surface of the exposed silicon substrate, and then the barrier layer is formed at the surface of the polysilicon gates; Step S2, the ions are implanted into the exposed substrate, and then several doped silicon regions are formed in the silicon substrate; Step S3, the doped silicon regions are etched to form the trench of U-shape, then the barrier layer is removed. The present invention protects the polysilicon gate and the substrate during the process of forming the trench. The rate of etching is increased and the productivity is improved and it is possible to control the depth of the U-shaped trench.
摘要翻译：本发明涉及CMOS半导体器件的制造。本发明包括：步骤S1，沉积覆盖多晶硅栅极的表面和硅衬底的暴露的上表面的氧化硅层，在暴露的硅衬底的上表面上去除氧化硅层，然后阻挡层形成在多晶硅栅极的表面; 步骤S2，将离子注入暴露的衬底中，然后在硅衬底中形成多个掺杂的硅区; 步骤S3，蚀刻掺杂的硅区域以形成U形沟槽，然后去除阻挡层。本发明在形成沟槽的过程中保护多晶硅栅极和衬底。蚀刻速率提高，生产率提高，并且可以控制U形沟槽的深度。

45. 发明授权

US08772157B2 Method of forming Cu interconnects 有权
标题翻译：形成铜互连的方法
公开(公告)号：US08772157B2
公开(公告)日：2014-07-08
申请号：US13667492
申请日：2012-11-02
申请人： Jingxun Fang
发明人： Jingxun Fang
IPC分类号： H01L21/768
CPC分类号： H01L21/7684 , H01L21/32115 , H01L21/3212
摘要： The present invention provides a method of forming Cu interconnects. The method comprises depositing an etch stop layer and an insulating layer subsequently; forming vias and trenches in the insulating layer; depositing a diffusion barrier layer and a copper seed layer using PVD; applying electroplating process to form the copper interconnects; depositing a layer of filling materials and reflowing the filling materials to eliminate the uneven surface topography of the copper interconnection layer; and applying annealing and CMP to planarize the top surface of the copper interconnects, and rinsing. According to the method of forming Cu interconnects, the uneven surface topography after electroplating can be reduced, and the surface topography after CMP can be planarized.
摘要翻译：本发明提供一种形成Cu互连的方法。该方法包括随后沉积蚀刻停止层和绝缘层; 在绝缘层中形成通孔和沟槽; 使用PVD沉积扩散阻挡层和铜籽晶层; 应用电镀工艺形成铜互连; 沉积一层填充材料并回流填充材料以消除铜互连层的不平坦表面形貌; 并且对退火和CMP进行平坦化以使铜互连的顶表面平坦化，并进行漂洗。根据形成Cu互连的方法，可以减少电镀后的不平坦表面形貌，并且CMP之后的表面形貌可以平坦化。

46. 发明申请

US20140153000A1 APPARATUS FOR DETECTING THE FLATNESS OF WAFER AND THE METHOD THEREOF 有权
标题翻译：用于检测波形平坦度的装置及其方法
公开(公告)号：US20140153000A1
公开(公告)日：2014-06-05
申请号：US14092056
申请日：2013-11-27
申请人： Shanghai Huali Microelectronics Corporation
发明人： WenLiang Li , LiJun Chen , Jun Zhu , HsuSheng Chang
IPC分类号： G01B11/30
CPC分类号： G01B11/306 , B24B37/042 , B24B37/105 , B24B37/30 , G01B11/303
摘要： An apparatus for detecting the flatness of a top surface of a wafer includes a plurality of detector elements, a metal sink and a plurality of injection pipes. Each detector element comprises: a metal tube body, jet pipes, a light receiver and a light emitter. The method comprises: injecting ultra-pure water into the detector elements by injection pipes; emitting parallel beams along an upward-oblique direction, a preset Angle θ being formed between the beams and the vertical direction. The radiated beams above the water surface are incident on a receiver. The intensity of the beams received by the light receiver is used to calculate the height of the detecting point of the surface of the silicon wafer to determine the flatness condition of the wafer surface. The flatness of the photo-resist covered on the wafer surface can also be accurately measured by this method.
摘要翻译：用于检测晶片的顶面的平坦度的装置包括多个检测器元件，金属槽和多个注入管。每个检测器元件包括：金属管体，喷射管，光接收器和发光器。该方法包括：通过注射管将超纯水注入检测器元件; 沿着向上倾斜的方向发射平行光束，预设的角度和角度; 形成在梁和垂直方向之间。水面以上的辐射光束入射到接收器上。由光接收器接收的光束的强度用于计算硅晶片表面的检测点的高度，以确定晶片表面的平坦度状态。也可以通过该方法精确地测量覆盖在晶片表面上的光致抗蚀剂的平坦度。

47. 发明申请

US20140077343A1 DUMMY WAFER STRUCTURE AND METHOD OF FORMING THE SAME 有权
标题翻译：疏水结构及其形成方法
公开(公告)号：US20140077343A1
公开(公告)日：2014-03-20
申请号：US13730576
申请日：2012-12-28
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Chuan REN , Zhi WANG , HsuSheng CHANG
IPC分类号： H01L29/06 , H01L21/02
CPC分类号： H01L29/0603 , C23C16/345 , C23C16/402 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/3205 , H01L21/32055
摘要： A dummy wafer structure and a method of forming the same are disclosed. The dummy wafer structure includes: a silicon substrate; a silicon nitride layer over the silicon substrate; and a silicon dioxide layer over the silicon nitride layer. The method includes: a first step of forming a silicon nitride layer over a silicon substrate so as to form a silicon-silicon nitride structure; and a second step of forming a silicon dioxide layer over the silicon-silicon nitride structure obtained in the first step so as to form a silicon-silicon nitride-silicon dioxide structure. Dummy wafers with this special structure are able to avoid deposition rate inconsistency in a polysilicon deposition process and are capable of avoiding conventional dummy wafers' adverse effect on deposit layer thicknesses of process wafers and hence providing the process wafers with deposit layers having a high inter-wafer uniformity.
摘要翻译：公开了一种虚设晶片结构及其形成方法。虚设晶片结构包括：硅衬底; 硅衬底上的氮化硅层; 以及氮化硅层上的二氧化硅层。该方法包括：在硅衬底上形成氮化硅层以形成硅 - 氮化硅结构的第一步骤; 以及在第一步骤中获得的硅 - 氮化硅结构上形成二氧化硅层以形成硅 - 氮化硅 - 二氧化硅结构的第二步骤。具有这种特殊结构的虚拟晶片能够避免多晶硅沉积工艺中的沉积速率不一致，并且能够避免常规的虚设晶片对工艺晶片的沉积层厚度的不利影响，并且因此为工艺晶片提供具有高间隔的沉积层，晶圆均匀性。

48. 发明授权

US08645879B2 Algorithm of Cu interconnect dummy inserting 有权
标题翻译：铜互连虚拟插入算法
公开(公告)号：US08645879B2
公开(公告)日：2014-02-04
申请号：US13731128
申请日：2012-12-31
申请人： Shanghai Huali Microelectronics Corporation
发明人： Jingxun Fang , Hsusheng Chang , Yungchieh Fan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlap; perform a logic operation on each square window; and divide the window into two parts: {circle around (1)} the area to-be-inserted; {circle around (2)} the non-inserting area; determine the metal density of the dummy pattern that should be inserted to each square window and the line width; determine the dummy pattern that should be inserted to the windows according to the metal density, line width, the pre-set dummy pattern and the layouting rules. The beneficial effects of the present invention is: avoided the shortcomings of fill density maximization in the rule-based filling method by using reasonable metal density and line width. And with a combination of the influence of line width and density to the copper plating process and chemical mechanical polishing morphology in model-based filling method, it can achieve a better planarization effect.
摘要翻译：本发明公开了一种Cu互连虚拟插入算法，包括：将半导体芯片的表面划分成几个方形窗口，其面积为A，每个窗口不重叠; 对每个方形窗口执行逻辑运算; 并将窗口分为两部分：{circle around（1）}要插入的区域; {round around（2）}非插入区域; 确定应插入每个正方形窗口的虚拟图案的金属密度和线宽度; 根据金属密度，线宽，预设的伪图案和布局规则确定应插入窗口的虚拟图案。本发明的有益效果是：通过使用合理的金属密度和线宽，避免了基于规则的填充方法中填充密度最大化的缺点。并结合线宽和密度对铜电镀工艺和化学机械抛光形态的影响，在基于模型的填充方法中，可以实现更好的平坦化效果。

49. 发明申请

US20130316470A1 METHOD WHICH CAN FORM CONTACT HOLES IN WAFER OF SEMICONDUCTOR 审中-公开
标题翻译：可以形成半导体波形接触孔的方法
公开(公告)号：US20130316470A1
公开(公告)日：2013-11-28
申请号：US13707485
申请日：2012-12-06
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Jun ZHOU
IPC分类号： H01L21/66
CPC分类号： H01L22/26 , H01L21/3086 , H01L21/76816 , H01L22/12 , H01L22/20
摘要： The present invention relates to the field of semiconductor integrated circuits, and particularly relates to a method which can form a contact hole in a wafer of semiconductor material. The invention has proposed a method which can form a contact hole in a wafer of semiconductor: measuring and comparing a Critical Dimension (CD) of a position corresponding to the contact hole in the hard mask with the CD required in the technology, and then, based on the measurement, adjusting the CD of the position corresponding to the contact hole in the hard mask, by conformal deposition or etching technology, to fit a requirement of the technology; the method can reduce process costs while improving production capacity.
摘要翻译：本发明涉及半导体集成电路领域，特别涉及能够在半导体材料的晶片中形成接触孔的方法。本发明提出了一种可以在半导体晶片中形成接触孔的方法：测量并比较与硬掩模中的接触孔相对应的位置的临界尺寸（CD）与该技术中所需的CD，基于测量，通过适形沉积或蚀刻技术调整与硬掩模中的接触孔相对应的位置的CD，以适应该技术的要求; 该方法可以在提高生产能力的同时降低工艺成本。

50. 发明申请

US20130273742A1 METHOD OF FORMING CONNECTION HOLES 有权
标题翻译：形成连接孔的方法
公开(公告)号：US20130273742A1
公开(公告)日：2013-10-17
申请号：US13721070
申请日：2012-12-20
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Yushu YANG , Cheng LI , Yuwen CHEN
IPC分类号： H01L21/306
CPC分类号： H01L21/30604 , H01L21/31116 , H01L21/76816
摘要： The present invention provides a method of forming connection holes. The method utilizes two different gases to perform two etching processes for the interlayer dielectric layer so as to form connection holes. The etching rate of the interlayer dielectric layer in the first etching process using the first etching gas is proportional to the size of the openings which defines the connection hole while the etching rate of the interlayer dielectric layer in the second etching process using the second etching gas is inversely related with size of the openings. According to the present invention, the first etching gas and the second etching gas compensate for each other to eliminate the loading effect, thus the connection holes are formed with almost the same depth. Therefore the damage of the etching stopper layer due to the high etching rate in the larger connection holes can be avoided, which prevents the excessive variation of the connecting resistance and expands the process window.
摘要翻译：本发明提供一种形成连接孔的方法。该方法利用两种不同的气体对层间电介质层进行两次蚀刻处理，形成连接孔。使用第一蚀刻气体的第一蚀刻工艺中的层间电介质层的蚀刻速率与限定连接孔的开口的尺寸成比例，而在使用第二蚀刻气体的第二蚀刻工艺中的层间电介质层的蚀刻速率与开口的尺寸成反比。根据本发明，第一蚀刻气体和第二蚀刻气体彼此补偿以消除负载效应，因此连接孔形成有几乎相同的深度。因此，可以避免由于较大的连接孔中的高蚀刻速率导致的蚀刻阻挡层的损伤，这防止了连接电阻的过度变化并扩大了工艺窗口。

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