会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 41. 发明授权
    • Article inspection device and inspection method
    • 物品检验装置及检验方法
    • US08406375B2
    • 2013-03-26
    • US13142712
    • 2010-12-28
    • Yigang YangTiezhu LiQinjiar ZhangYi ZhangYingkang JinQinghao ChenYuanjing LiYinong Liu
    • Yigang YangTiezhu LiQinjiar ZhangYi ZhangYingkang JinQinghao ChenYuanjing LiYinong Liu
    • G01N23/201
    • G01V5/0016G01N23/046G01N23/05G01N2223/419G01V5/0025
    • The present invention discloses an article inspection device, comprising: an x-ray machine, a collimation unit, a transmission detector array and a scattering detector array. The scattering detector array comprising a plurality of same scattering detector modules arranged in a matrix of i-rows and j-columns. A transmission cross section of the article transmitted by the x-rays is divided into a plurality of same sub-regions arranged in a matrix of i-rows and j-columns. The plurality of scattering detector modules arranged in i-rows and j-columns correspond to the plurality of sub-regions arranged in i-rows and j-columns one by one for detecting pair production effect annihilation photons and Compton-effect scattering photons from the respective sub-regions. Obtaining atomic numbers of the respective sub-regions based on a ratio of the pair production effect annihilation photon count to the Compton-effect scattering photon count, so as to form a three-dimensional image of the article. In addition, the present invention further discloses an article inspection method.
    • 本发明公开了一种物品检查装置,包括:x射线机,准直单元,透射检测器阵列和散射检测器阵列。 散射检测器阵列包括以i行和j列的矩阵排列的多个相同的散射检测器模块。 通过X射线透射的物品的透射截面被划分成以i行和j列的矩阵排列的多个相同的子区域。 布置在i行和j列中的多个散射检测器模块对应于一排一列地排列在i行和j列中的多个子区域,用于检测来自该对象的生成效应湮灭光子和康普顿效应散射光子 各分区域。 基于对生产效应湮灭光子计数与康普顿效应散射光子计数的比率,获得各个子区域的原子序数,以形成物品的三维图像。 此外,本发明还公开了一种物品检查方法。
    • 42. 发明授权
    • Systems and methods for storing data in a multi-level cell solid state storage device
    • 用于在多级单元固态存储设备中存储数据的系统和方法
    • US08402203B2
    • 2013-03-19
    • US12650712
    • 2009-12-31
    • Todd Ray Strope
    • Todd Ray Strope
    • G06F12/00
    • G06F12/0246G06F2212/7202
    • This disclosure is related to systems and methods for storing data in multi-level cell solid state storage devices, such as Flash memory devices. In one example, a multi-level cell memory array has programmable pages, a first page having a first programming time, and a second page having a second programming time that is different than the first programming time. In one embodiment, the first programming time is faster than the second programming time. Further, a controller coupled to the multi-level cell memory array may be configured to select the first page to store the data when a priority level of a write operation indicates a first priority level and select the second page to store the data when the priority level indicates a second priority level.
    • 本公开涉及用于在诸如闪存设备的多级单元固态存储设备中存储数据的系统和方法。 在一个示例中,多级单元存储器阵列具有可编程页面,具有第一编程时间的第一页面和具有与第一编程时间不同的第二编程时间的第二页面。 在一个实施例中,第一编程时间比第二编程时间快。 此外,耦合到多级单元存储器阵列的控制器可以被配置为当写操作的优先级指示第一优先级时选择第一页来存储数据,并且当优先级选择第二页以存储数据时 级别表示第二优先级。
    • 43. 发明授权
    • Total air temperature probe and method for reducing de-icing/anti-icing heater error
    • 总空气温度探头和减少除冰/防冰加热器误差的方法
    • US08392141B2
    • 2013-03-05
    • US12610804
    • 2009-11-02
    • Scott John Wigen
    • Scott John Wigen
    • G01K15/00G01F13/00G01P5/00
    • G01K13/02G01K7/42G01K15/005G01K2013/024
    • A method of reducing de-icing heater error (DHE) in total air temperature (TAT) probes is provided. Using the method, a nominal DHE function is obtained for a particular type of TAT probe, with the nominal DHE function having been derived from a plurality of TAT probes of the particular type. A probe specific correction coefficient is calculated for an individual TAT probe of the particular type as a function of a measured DHE at a first airflow and a predicted DHE at the first airflow. The predicted DHE at the first airflow is determined using the nominal DHE function derived from the plurality of TAT probes of the particular type. The probe specific correction coefficient is then stored for later use, or used to determine DHE with the individual TAT probe over a range of airflows as a function of the probe specific correction coefficient.
    • 提供了一种减少总空气温度(TAT)探头中除冰加热器误差(DHE)的方法。 使用该方法,获得针对特定类型的TAT探针的标称DHE功能,其中额定DHE功能已经从特定类型的多个TAT探针导出。 针对特定类型的单个TAT探针计算探针特定校正系数,作为在第一气流下测量的DHE和在第一气流处的预测DHE的函数。 使用从特定类型的多个TAT探针导出的标称DHE函数确定第一气流处的预测DHE。 然后将探针特异性校正系数存储以供以后使用,或用于根据探针特异性校正系数在单个TAT探针的范围内确定DHE。
    • 47. 发明授权
    • Method for integrating replacement gate in semiconductor device
    • 在半导体器件中集成替换栅极的方法
    • US08377769B2
    • 2013-02-19
    • US13379169
    • 2011-08-02
    • Gaobo XuQiuxia Xu
    • Gaobo XuQiuxia Xu
    • H01L21/8238
    • H01L29/66545H01L21/823842
    • A method for integrating a replacement gate in a semiconductor device is disclosed. The method may comprise: forming a well region on a semiconductor substrate, and defining a N-type device region and/or a P-type device region; forming a sacrificial gate stack or sacrificial gate stacks respectively on the N-type device region and/or the P-type device region, the sacrificial gate stack or each of the sacrificial gate stacks comprising a sacrificial gate dielectric layer and a sacrificial gate electrode layer, wherein the sacrificial gate dielectric layer is disposed on the semiconductor substrate, and the sacrificial gate electrode layer is disposed on the sacrificial gate dielectric layer; forming a spacer or spacers surrounding the sacrificial gate stack or the respective sacrificial gate stacks; forming source/drain regions on both sides of the sacrificial gate stack or the respective sacrificial gate stacks and embedded into the semiconductor substrate; forming a SiO2 layer on the semiconductor substrate; forming a SOG layer on the SiO2 layer; etching the SOG layer until the SiO2 layer is exposed; etching the SOG layer and the SiO2 layer at different rates in such a manner that the SiO2 layer is planarized; and forming a N-type replacement gate stack on the N-type device region and/or a P-type replacement gate stack on the P-type device region, respectively.
    • 公开了一种在半导体器件中集成置换栅极的方法。 该方法可以包括:在半导体衬底上形成阱区,并且限定N型器件区和/或P型器件区; 在N型器件区域和/或P型器件区域上分别形成牺牲栅极堆叠或牺牲栅极堆叠,牺牲栅极堆叠或每个牺牲栅极堆叠包括牺牲栅极电介质层和牺牲栅极电极层 其中所述牺牲栅极电介质层设置在所述半导体衬底上,并且所述牺牲栅极电极层设置在所述牺牲栅极电介质层上; 形成围绕所述牺牲栅极叠层或相应的牺牲栅极叠层的间隔物或间隔物; 在牺牲栅极堆叠或相应的牺牲栅极堆叠的两侧上形成源极/漏极区域并嵌入到半导体衬底中; 在所述半导体衬底上形成SiO 2层; 在SiO 2层上形成SOG层; 蚀刻SOG层直到暴露SiO 2层; 以使SiO 2层平坦化的方式以不同的速率蚀刻SOG层和SiO 2层; 以及分别在P型器件区域上的N型器件区域和/或P型替换栅极堆叠上形成N型替换栅极堆叠。