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41. 发明申请

US20110316080A1 FIN TRANSISTOR STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译： FIN晶体管结构及其制造方法
公开(公告)号：US20110316080A1
公开(公告)日：2011-12-29
申请号：US12937486
申请日：2010-06-24
申请人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
发明人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/7851 , H01L29/66795
摘要： There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer.
摘要翻译：提供鳍式晶体管结构及其制造方法。翅片晶体管结构包括形成在半导体衬底上的鳍片，其中在用作晶体管结构的沟道区域的鳍片的一部分和衬底之间形成绝缘材料，并且在半导体衬底的剩余部分之间形成体半导体材料翅片和底物。由此，可以在保持低成本，高热传递等优点的同时，减小电流泄漏。

42. 发明申请

US20110298018A1 TRANSISTOR AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：晶体管及其制造方法
公开(公告)号：US20110298018A1
公开(公告)日：2011-12-08
申请号：US12937502
申请日：2010-06-28
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/28105 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： The invention provides a transistor, including: a substrate having a channel region; a source region and a drain region on two ends of the channel region of the substrate respectively; a gate high-K dielectric layer on a top surface of the substrate above the channel region between the source region and the drain region; an interfacial layer under the gate high-K dielectric layer, including a first portion near the source region and a second portion near the drain region, wherein an equivalent oxide thickness of the first portion is larger than that of the second portion. An asymmetric replacement metal gate forms an asymmetric interfacial layer, which is thin at the drain region side and thick at the source region side. At the thin drain region side, the short channel effect is significant and the asymmetric interfacial layer advantageously suppresses the short channel effect. At the thick source region side, the carrier mobility has a large influence on the device, and the asymmetric interfacial layer prevents the carrier mobility from decreasing. Further, the asymmetric replacement metal gate implements an asymmetric metal work function.
摘要翻译：本发明提供一种晶体管，包括：具有沟道区的衬底; 分别在所述衬底的沟道区域的两端上的源极区域和漏极区域; 位于源极区域和漏极区域之间的沟道区域上方的衬底顶表面上的栅极高K电介质层; 在栅极高K电介质层下面的界面层，包括靠近源区的第一部分和靠近漏极区的第二部分，其中第一部分的等效氧化物厚度大于第二部分的等效氧化物厚度。不对称替代金属栅极形成不对称界面层，其在漏极区侧较薄，在源极区侧较厚。在薄漏极侧，短沟道效应显着，不对称界面层有利地抑制了短沟道效应。在较厚的源极侧，载流子迁移率对器件的影响较大，不对称界面层阻止载流子迁移率降低。此外，不对称替代金属栅极实现了非对称金属功能。

43. 发明申请

US20110291184A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20110291184A1
公开(公告)日：2011-12-01
申请号：US13062911
申请日：2010-09-26
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/336 , B82Y99/00
CPC分类号： H01L29/78687 , H01L29/66545 , H01L29/66621 , H01L29/66772
摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate; an epitaxial semiconductor layer formed on two side portions of the semiconductor substrate; a gate stack formed at a central position on the semiconductor substrate and abutting the epitaxial semiconductor layer, the gate comprising a gate conductor layer and a gate dielectric layer which is sandwiched between the gate conductor layer and the semiconductor substrate and surrounding the lateral surfaces of the gate conductor layer; and a sidewall spacer formed on the epitaxial semiconductor layer and surrounding the gate. The method for manufacturing the above semiconductor structure comprises forming raised source/drain regions in the epitaxial semiconductor layer utilizing the sacrificial gate. The semiconductor structure and the method for manufacturing the same can simplify the fabrication process for an ultra-thin SOI transistor and reduce the ON-state resistance and power consumption of the transistor.
摘要翻译：本申请公开了一种半导体结构及其制造方法。半导体结构包括半导体衬底; 形成在所述半导体衬底的两个侧面上的外延半导体层; 形成在所述半导体衬底上的中心位置并与所述外延半导体层邻接的栅极叠层，所述栅极包括栅极导体层和栅极电介质层，所述栅极介电层夹在所述栅极导体层和所述半导体衬底之间，栅极导体层; 以及形成在外延半导体层上并围绕栅极的侧壁间隔物。制造上述半导体结构的方法包括利用牺牲栅极在外延半导体层中形成凸起的源/漏区。半导体结构及其制造方法可以简化超薄SOI晶体管的制造工艺，并降低晶体管的导通电阻和功耗。

44. 发明申请

US20110260258A1 FIELD EFFECT TRANSISTOR DEVICE WITH IMPROVED CARRIER MOBILITY AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有改进的载波移动性的场效应晶体管装置及其制造方法
公开(公告)号：US20110260258A1
公开(公告)日：2011-10-27
申请号：US13063731
申请日：2010-06-22
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L29/7845
摘要： The devices are manufactured by replacement gate process and replacement sidewall spacer process, and both tensile stress in the channel region of NMOS device and compressive stress in the channel region of PMOS device are increased by forming a first stress layer with compressive stress in the space within the first metal gate layer of NMOS and a second stress layer with tensile stress in the space within the second metal gate layer of PMOS, respectively. After formation of the stress layers, sidewall spacers of the gate stacks of PMOS and NMOS devices are removed so as to release stress in the channel regions. In particular, stress structure with opposite stress may be formed on sidewalls of the gate stacks of the NMOS device and PMOS device and on a portion of the source region and the drain region, in order to further increase both tensile stress of the NMOS device and compressive stress of the PMOS device.
摘要翻译：器件通过更换栅极工艺和替换侧壁间隔工艺制造，NMOS器件的沟道区域中的拉伸应力和PMOS器件的沟道区域中的压应力均增加，在第一应力层内形成压缩应力 NMOS的第一金属栅极层和在PMOS的第二金属栅极层内的空间中具有拉伸应力的第二应力层。在形成应力层之后，去除PMOS和NMOS器件的栅叠层的侧壁间隔物，以释放沟道区中的应力。特别地，具有相反应力的应力结构可以形成在NMOS器件和PMOS器件的栅极堆叠的侧壁上，并且在源极区域和漏极区域的一部分上形成，以便进一步增加NMOS器件的拉伸应力和 PMOS器件的压应力。

45. 发明申请

US20110193166A1 STRUCTURE AND METHOD FOR REDUCING FLOATING BODY EFFECT OF SOI MOSFETS 有权
标题翻译：降低SOI MOSFET浮体效应的结构和方法
公开(公告)号：US20110193166A1
公开(公告)日：2011-08-11
申请号：US12700797
申请日：2010-02-05
申请人： Qingqing LIANG , Huilong ZHU , Zhijiong LUO , Haizhou YIN
发明人： Qingqing LIANG , Huilong ZHU , Zhijiong LUO , Haizhou YIN
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L29/6675 , H01L29/78615 , H01L29/78624 , H01L29/78687
摘要： The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). An integrated circuit (IC) structure includes an SOI substrate and at least one MOSFET formed on the SOI substrate. Additionally, the IC structure includes an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET.
摘要翻译：本发明一般涉及半导体结构和方法，更具体地说，涉及用于减少绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）的浮体效应的结构和方法。集成电路（IC）结构包括SOI衬底和形成在SOI衬底上的至少一个MOSFET。此外，IC结构包括通过损坏pn结在至少一个MOSFET中的不对称源极 - 漏极结，以减少至少一个MOSFET的浮体效应。

46. 发明申请

US20110169088A1 STRUCTURE AND METHOD HAVING ASYMMETRICAL JUNCTION OR REVERSE HALO PROFILE FOR SEMICONDUCTOR ON INSULATOR (SOI) METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) 失效
标题翻译：具有绝缘体（SOI）金属氧化物半导体场效应晶体管（MOSFET）的半导体的非对称结或反向HALO分布的结构和方法
公开(公告)号：US20110169088A1
公开(公告)日：2011-07-14
申请号：US12686402
申请日：2010-01-13
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L27/1207 , H01L21/76251 , H01L21/8221 , H01L27/0688 , H01L29/66545
摘要： A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided.
摘要翻译：提供了一种装置和方法，在一个实施例中提供了第一半导体器件，其包括在第一沟道区上的第一栅极结构，其中第一源区和第一漏区存在于第一沟道区的相对侧上，其中金属氮化物间隔物仅存在于第一沟道区的一侧。该器件还包括在第二沟道区上包括第二栅极结构的第二半导体器件，其中第二源区和第二漏区存在于第二沟道区的相对侧上。可以存在互连件，其提供第一半导体器件和第二半导体器件之间的电连通，其中第一半导体器件和第二半导体器件中的至少一个被反转。还提供了具有反向卤素掺杂剂分布的结构。

47. 发明申请

US20100219485A1 FORMATION OF RAISED SOURCE/DRAIN STUCTURES IN NFET WITH EMBEDDED SIGE IN PFET 有权
标题翻译：在PFET中嵌入信号的NFET中形成上升的源/漏极结构
公开(公告)号：US20100219485A1
公开(公告)日：2010-09-02
申请号：US12780962
申请日：2010-05-17
申请人： Yung Fu CHONG , Zhijiong LUO , Joo Chan KIM , Judson Robert HOLT
发明人： Yung Fu CHONG , Zhijiong LUO , Joo Chan KIM , Judson Robert HOLT
IPC分类号： H01L27/092 , H01L27/088
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.
摘要翻译：用于在NFET器件中形成凸起的源极/漏极结构并在PFET器件中形成嵌入的SiGe源极/漏极的结构和方法。我们在衬底上的NFET区域和PFET区域上的PFET栅极结构提供NFET栅极结构。我们提供与NFET栅极相邻的NFET SDE区域，并提供与PFET栅极相邻的PFET SDE区域。我们在邻近PFET第二间隔物的衬底中的PFET区域中形成凹陷。我们在凹槽中形成PFET嵌入式源极/漏极应力器。我们在NFET SDE区域上形成NFET S / D外延Si层，并在PFET嵌入式源极/漏极应力器上形成PFET S / D外延Si层。在随后的自对准硅化物步骤中，在PFET嵌入式源极/漏极应力源上的外延Si层被消耗，以在PFET嵌入式源极/漏极应力器上形成稳定和低电阻率的硅化物。我们通过将N型离子注入到与NFET栅极结构相邻的NFET区域中并进入NFET S / D应力Si层来形成NFET S / D注入，以形成升高的NFET源极/漏极。

48. 发明授权

US07767579B2 Protection of SiGe during etch and clean operations 失效
标题翻译：在蚀刻和清洁操作期间保护SiGe
公开(公告)号：US07767579B2
公开(公告)日：2010-08-03
申请号：US11954802
申请日：2007-12-12
申请人： Ashima B Chakravarti , Zhijiong Luo , Renee Tong Mo , Shreesh Narasimha , Katsunori Onishi
发明人： Ashima B Chakravarti , Zhijiong Luo , Renee Tong Mo , Shreesh Narasimha , Katsunori Onishi
IPC分类号： H01L21/44 , H01L21/31 , H01L21/469
CPC分类号： H01L21/823807 , H01L21/02233 , H01L21/02252 , H01L21/31658 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method of making a semiconductor device includes forming a transistor structure having one of an embedded epitaxial stressed material in a source and drain region and a stressed channel and well, subjecting the transistor structure to plasma oxidation, and removing spacer material from the transistor structure.
摘要翻译：制造半导体器件的方法包括形成在源极和漏极区域中具有嵌入式外延应力材料之一的晶体管结构以及受应力的沟道和阱，对晶体管结构进行等离子体氧化，以及从晶体管结构去除间隔物材料。

49. 发明授权

US07741658B2 Self-aligned super stressed PFET 有权
标题翻译：自对准超应力PFET
公开(公告)号：US07741658B2
公开(公告)日：2010-06-22
申请号：US11842437
申请日：2007-08-21
申请人： Yaocheng Liu , Zhijiong Luo , Huilong Zhu
发明人： Yaocheng Liu , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L31/0328
CPC分类号： H01L21/26506 , H01L21/268 , H01L29/1054 , H01L29/165 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth.
摘要翻译：本发明的实施例包括自对准超应力p型场效应晶体管（PFET）。更具体地，场效应晶体管包括包含N掺杂材料的沟道区和沟道区上方的栅。场效应晶体管还包括在沟道区的第一侧上的源极区域和与第一侧相对的沟道区域的第二侧上的漏极区域。源极和漏极区域各自包含硅锗，其中硅锗具有外延生长的结构标记。

50. 发明授权

US07691690B2 Methods for forming dual fully silicided gates over fins of FinFet devices 有权
标题翻译：在FinFet设备的翅片上形成双完全硅化栅的方法
公开(公告)号：US07691690B2
公开(公告)日：2010-04-06
申请号：US11622586
申请日：2007-01-12
申请人： Huilong Zhu , Zhijiong Luo
发明人： Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/00
CPC分类号： H01L29/66795 , H01L29/785
摘要： Methods for forming fully silicided gates over fins of FinFet devices are disclosed. The disclosure provides methods for patterning a gate stack over each fin from a polysilicon layer and a polysilicon germanium layer, and then removing the polysilicon germanium layer over one of the fins. The disclosure further includes forming a metal layer over both fins and annealing the FinFet device to form fully silicided gates over each fin of the FinFet device.
摘要翻译：公开了在FinFet装置的翅片上形成完全硅化栅的方法。本公开提供了用于从多晶硅层和多晶硅锗层在每个鳍上形成栅叠层的方法，然后在一个鳍上去除多晶硅锗层。本公开还包括在两个翅片上形成金属层并退火FinFet器件以在FinFet器件的每个鳍上形成完全硅化的栅极。

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