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41. 发明授权

US09318561B2 Device isolation for III-V substrates 有权
标题翻译： III-V基板的器件隔离
公开(公告)号：US09318561B2
公开(公告)日：2016-04-19
申请号：US14298421
申请日：2014-06-06
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy M. Cohen
IPC分类号： H01L33/00 , H01L29/205 , H01L21/02 , H01L21/3065 , H01L29/06
CPC分类号： H01L29/205 , H01L21/02178 , H01L21/02241 , H01L21/02461 , H01L21/02463 , H01L21/02488 , H01L21/02502 , H01L21/0251 , H01L21/02543 , H01L21/02546 , H01L21/30612 , H01L21/3065 , H01L21/762 , H01L21/823431 , H01L21/8252 , H01L29/0684 , H01L29/207
摘要： Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.
摘要翻译：提供了用于III-V半导体衬底的器件隔离技术。一方面，提供一种制造III-V半导体器件的方法。该方法包括以下步骤：提供具有铟磷化物（InP）层的衬底; 在InP就绪层上形成铁（Fe）掺杂的InP层; 在Fe掺杂的InP层上形成外延III-V半导体材料层; 以及图案化所述外延III-V半导体材料层以形成所述器件的一个或多个有效区域。还提供III-V半导体器件。

42. 发明申请

US20160079421A1 FIN FIELD EFFECT TRANSISTOR INCLUDING SELF-ALIGNED RAISED ACTIVE REGIONS 有权
公开(公告)号：US20160079421A1
公开(公告)日：2016-03-17
申请号：US14945912
申请日：2015-11-19
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy M. Cohen , Amlan Majumdar
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/20 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/6681 , H01L29/7841 , H01L29/785
摘要： Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures. Employing the disposable gate structure and the gate spacer as an etch mask, physically exposed portions of the fin mask structures and the semiconductor material portion are removed by an etch. A source region and a drain region are formed by selective epitaxy of a semiconductor material from physically exposed surfaces of the crystalline insulator layer. The disposable gate structure is removed selective to the source region and the drain region. Semiconductor fins are formed by anisotropically etching portions of the semiconductor material portion, employing the gate spacer and the fin mask structures as etch masks. A gate dielectric and a gate electrode are formed within the gate cavity.

43. 发明授权

US09263464B2 Field effect transistors including contoured channels and planar channels 有权
标题翻译：场效应晶体管，包括轮廓通道和平面通道
公开(公告)号：US09263464B2
公开(公告)日：2016-02-16
申请号：US14269525
申请日：2014-05-05
申请人： International Business Machines Corporation
发明人： Anirban Basu , Pouya Hashemi
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/84 , H01L21/845 , H01L27/1211 , H01L29/66545 , H01L29/78696
摘要： Disposable gate structures and a planarization dielectric layer are formed over doped semiconductor material portions on a crystalline insulator layer. Gate cavities are formed by removing the disposable gate structures selective to the planarization dielectric layer. Doped semiconductor material portions are removed from underneath the gate cavities to provide pairs of source and drain regions separated by a gate cavity. Within a first gate cavity, a faceted crystalline dielectric material portion is grown from a physically exposed surface of the crystalline insulator layer, while a second gate is temporarily coated with an amorphous material layer. A contoured semiconductor region is epitaxially grown on the faceted crystalline dielectric material portion in the first gate cavity, while a planar semiconductor region is epitaxially grown in the second gate cavity. The semiconductor regions can provide at least one contoured channel region and at least one planar channel region.
摘要翻译：在结晶绝缘体层上的掺杂半导体材料部分上形成一次性栅极结构和平坦化介电层。通过去除对平坦化介电层有选择性的一次性栅极结构来形成栅极腔。掺杂的半导体材料部分从栅极腔下方移除以提供由栅极腔分隔开的一对源极和漏极区域。在第一栅极腔内，从结晶绝缘体层的物理暴露表面生长刻面晶体介电材料部分，而第二栅极暂时涂覆有非晶材料层。在第一栅腔中的刻面结晶介质材料部分上外延生长成像半导体区域，而平面半导体区域在第二栅极腔中外延生长。半导体区域可以提供至少一个轮廓通道区域和至少一个平面通道区域。

44. 发明申请

US20150372141A1 SILICON-CONTAINING, TUNNELING FIELD-EFFECT TRANSISTOR INCLUDING III-N SOURCE 有权
标题翻译：含硅，隧道场效应晶体管，包括III-N源
公开(公告)号：US20150372141A1
公开(公告)日：2015-12-24
申请号：US14311401
申请日：2014-06-23
申请人： International Business Machines Corporation
发明人： Anirban Basu , Bahman Hekmatshoartabari , Davood Shahrjerdi
IPC分类号： H01L29/78 , H01L29/04 , H01L29/267 , H01L29/66 , H01L21/308 , H01L21/02 , H01L29/10 , H01L21/28 , H01L29/08 , H01L21/265 , H01L29/06 , H01L21/306
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/0254 , H01L21/02576 , H01L21/26506 , H01L21/26586 , H01L21/28255 , H01L21/30604 , H01L21/30608 , H01L21/308 , H01L21/3085 , H01L29/04 , H01L29/045 , H01L29/0657 , H01L29/083 , H01L29/0847 , H01L29/1033 , H01L29/1041 , H01L29/267 , H01L29/66477 , H01L29/66977 , H01L29/7391
摘要： Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.
摘要翻译：包括硅，锗或硅锗通道和III-N源极区域的隧道化场效应晶体管用于低功率操作。由晶体管的源极和沟道区域形成断带异质结。制造方法包括硅衬底的选择性各向异性湿蚀刻，然后III-N材料的外延沉积和/或衬底的锗注入，然后III-N材料的外延沉积。

45. 发明授权

US09150434B2 Electricity-less water disinfection 有权
标题翻译：无电水消毒
公开(公告)号：US09150434B2
公开(公告)日：2015-10-06
申请号：US13673520
申请日：2012-11-09
申请人： International Business Machines Corporation
发明人： Anirban Basu , Stephen W. Bedell , Devendra K. Sadana
IPC分类号： C02F1/32 , A61L2/00 , A61L9/00
CPC分类号： C02F1/325 , A61L2/00 , A61L9/00 , C02F2201/009 , C02F2201/3222 , C02F2201/3227 , C02F2303/04 , C02F2307/02 , C02F2307/04 , Y02A20/212
摘要： Disinfecting a sample of water includes generating a current using an array of photovoltaic cells, using the current to power an array of light emitting diodes, wherein the array of light emitting diodes emits a germicidal wavelength of radiation, and exposing the sample of water to the radiation. Another method for disinfecting a sample of water includes placing the sample of water within a container, wherein the container includes an array of photovoltaic cells encircling an exterior wall of the container and an array of light emitting diodes encircling an interior wall of the container, placing the container in a location exposed to solar radiation, converting the solar radiation to a current using the array of photovoltaic cells, and powering the array of light emitting diodes using the current, wherein the array of light emitting diodes emits a germicidal wavelength of radiation sufficient to disinfect the sample of water.
摘要翻译：消毒水样包括使用光伏电池阵列产生电流，使用电流为发光二极管阵列供电，其中发光二极管阵列发射杀菌波长的辐射，并将水样品暴露于辐射。用于对水样品进行消毒的另一种方法包括将水样品放置在容器内，其中容器包括围绕容器外壁的光伏电池阵列和环绕容器内壁的发光二极管阵列，放置所述容器处于暴露于太阳辐射的位置，使用所述光伏电池阵列将所述太阳辐射转换成电流，以及使用所述电流对所述发光二极管阵列供电，其中所述发光二极管阵列发射足够的辐射的杀菌波长对水样进行消毒。

46. 发明申请

US20150255570A1 FIN FIELD EFFECT TRANSISTOR INCLUDING SELF-ALIGNED RAISED ACTIVE REGIONS 有权
标题翻译： FIN场效应晶体管，包括自对准的激活区域
公开(公告)号：US20150255570A1
公开(公告)日：2015-09-10
申请号：US14200851
申请日：2014-03-07
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy M. Cohen , Amlan Majumdar
IPC分类号： H01L29/66 , H01L29/20 , H01L29/78
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/20 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/6681 , H01L29/7841 , H01L29/785
摘要： Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures. Employing the disposable gate structure and the gate spacer as an etch mask, physically exposed portions of the fin mask structures and the semiconductor material portion are removed by an etch. A source region and a drain region are formed by selective epitaxy of a semiconductor material from physically exposed surfaces of the crystalline insulator layer. The disposable gate structure is removed selective to the source region and the drain region. Semiconductor fins are formed by anisotropically etching portions of the semiconductor material portion, employing the gate spacer and the fin mask structures as etch masks. A gate dielectric and a gate electrode are formed within the gate cavity.
摘要翻译：在晶体绝缘体层上的半导体材料部分上形成翅片掩模结构。在翅片掩模结构上形成一次性栅极结构和栅极间隔物。使用一次性栅极结构和栅极间隔物作为蚀刻掩模，通过蚀刻去除鳍式掩模结构和半导体材料部分的物理暴露部分。通过从晶体绝缘体层的物理暴露表面选择性地外延半导体材料来形成源极区和漏极区。一次性栅极结构被选择性地去除源极区域和漏极区域。半导体翅片通过各向异性蚀刻半导体材料部分的部分，采用栅极间隔物和鳍状掩模结构作为蚀刻掩模来形成。栅极电介质和栅电极形成在栅极腔内。

47. 发明授权

US09129825B2 Field effect transistor including a regrown contoured channel 有权
标题翻译：场效应晶体管包括重新形成的轮廓通道
公开(公告)号：US09129825B2
公开(公告)日：2015-09-08
申请号：US14070038
申请日：2013-11-01
申请人： International Business Machines Corporation
发明人： Anirban Basu , Pouya Hashemi , Ali Khakifirooz
IPC分类号： H01L27/02 , H01L21/20 , H01L29/06 , H01L29/78 , H01L29/66 , H01L21/762
CPC分类号： H01L29/0653 , H01L21/7624 , H01L29/66545 , H01L29/66772 , H01L29/78 , H01L29/7853 , H01L29/78696
摘要： At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A faceted crystalline dielectric material portion is grown from a physically exposed surface of the crystalline insulator layer. A contoured channel region is epitaxially grown on the faceted crystalline dielectric material portion. The contoured channel region increases the distance that charge carriers travel relative to a separation distance between the source region and the drain region.
摘要翻译：在结晶绝缘体层上形成至少一个掺杂半导体材料区域。在所述至少一个掺杂半导体材料区域上形成一次性栅极结构和横向围绕所述一次性栅极结构的平坦化介电层。一次性栅极结构被选择性地移除到平坦化介电层以形成栅极腔。至少一个掺杂半导体材料区域的部分从栅极腔下面去除。至少一个掺杂半导体材料区域的剩余部分构成源极区域和漏极区域。从结晶绝缘体层的物理暴露的表面生长刻面的结晶介电材料部分。在刻面的结晶介电材料部分上外延生长轮廓通道区域。轮廓通道区域增加了电荷载流子相对于源极区域和漏极区域之间的间隔距离行进的距离。

48. 发明授权

US09070770B2 Low interfacial defect field effect transistor 有权
标题翻译：低界面缺陷场效应晶体管
公开(公告)号：US09070770B2
公开(公告)日：2015-06-30
申请号：US14010585
申请日：2013-08-27
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy Cohen , Amlan Majumdar
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/42356 , H01L21/28026 , H01L21/283 , H01L29/1054 , H01L29/201 , H01L29/41783 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/78696
摘要： A disposable gate structure straddling a semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask. A planarization dielectric layer is formed such that a top surface of the planarization dielectric layer is coplanar with the disposable gate structure. A gate cavity is formed by removing the disposable gate structure. An epitaxial cap layer is deposited on physically exposed semiconductor surfaces of the semiconductor fin by selective epitaxy. A gate dielectric layer is formed on the epitaxial cap layer, and a gate electrode can be formed by filling the gate cavity. The epitaxial cap layer can include a material that reduces the density of interfacial defects at an interface with the gate dielectric layer.
摘要翻译：形成跨越半导体鳍片的一次性栅极结构。使用一次性栅极结构作为注入掩模形成源区和漏区。形成平坦化介电层，使得平坦化电介质层的顶表面与一次性栅极结构共面。通过去除一次性栅极结构形成栅极腔。外延盖层通过选择性外延沉积在半导体鳍片的物理暴露的半导体表面上。在外延盖层上形成栅极电介质层，并且可以通过填充栅极腔来形成栅电极。外延盖层可以包括降低与栅极介电层的界面处的界面缺陷密度的材料。

49. 发明申请

US20150021662A1 III-V SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACTS 有权
标题翻译：具有自对准触点的III-V半导体器件
公开(公告)号：US20150021662A1
公开(公告)日：2015-01-22
申请号：US13945281
申请日：2013-07-18
申请人： International Business Machines Corporation
发明人： Anirban Basu , Amlan Majumdar , Yanning Sun
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/66462 , H01L29/205 , H01L29/41775 , H01L29/4236 , H01L29/7784 , H01L29/78
摘要： A method including forming a III-V compound semiconductor-containing heterostructure, forming a gate dielectric having a dielectric constant greater than 4.0 positioned within a gate trench, the gate trench formed within the III-V compound semiconductor-containing heterostructure, and forming a gate conductor within the gate trench on top of the gate dielectric, the gate conductor extending above the III-V compound semiconductor heterostructure. The method further including forming a pair of sidewall spacers along opposite sides of a portion of the gate conductor extending above the III-V compound semiconductor-containing heterostructure and forming a pair of source-drain contacts self-aligned to the pair of sidewall spacers.
摘要翻译：一种包括形成含III-V族化合物半导体的异质结构的方法，形成位于栅沟槽内的介电常数大于4.0的栅极电介质，形成在含III-V族化合物半导体的异质结构内的栅极沟槽，并形成栅极导体在栅极电介质顶部的栅极沟槽内，栅极导体延伸到III-V族化合物半导体异质结构之上。所述方法还包括沿着在III-V族化合物半导体的异质结构之上延伸的栅极导体的一部分的相对侧形成一对侧壁间隔物，并且形成一对与所述一对侧壁间隔物自对准的源极 - 漏极接触。

50. 发明授权

US08937299B2 III-V finFETs on silicon substrate 有权
标题翻译：硅衬底上的III-V finFET
公开(公告)号：US08937299B2
公开(公告)日：2015-01-20
申请号：US13967102
申请日：2013-08-14
申请人： International Business Machines Corporation
发明人： Anirban Basu , Cheng-Wei Cheng , Amlan Majumdar , Ryan M. Martin , Uzma Rana , Devendra K. Sadana , Kuen-Ting Shiu , Yanning Sun
IPC分类号： H01L29/78 , H01L29/267 , H01L29/49 , H01L29/51
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.
摘要翻译：一种用于形成鳍状场效应晶体管的方法，包括在硅衬底上形成电介质层，在电介质层中形成高达纵横比的沟槽直至衬底，高纵横比包括大于或等于1:1的高宽比;以及使用纵横比捕获工艺在沟槽中外延生长含硅的半导体材料以形成翅片。蚀刻一个或多个电介质层以暴露鳍片的一部分。在翅片的一部分上外延生长阻挡层，在鳍片上方形成栅叠层。围绕翅片和门叠层的部分形成间隔件。将掺杂剂植入翅片的部分。源极和漏极区域使用非含硅半导体材料生长在翅片上。

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