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41. 发明授权

US08957479B2 Formation of multi-height MUGFET 有权
标题翻译：形成多高度MUGFET
公开(公告)号：US08957479B2
公开(公告)日：2015-02-17
申请号：US13933356
申请日：2013-07-02
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L29/78 , H01L27/088 , H01L21/8234 , H01L29/66 , H01L27/12
CPC分类号： H01L29/7831 , H01L21/823431 , H01L21/823456 , H01L27/1203 , H01L29/66795 , H01L29/785
摘要： A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure and a second rectangular fin structure, both positioned on a substrate. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. A gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure. The gate conductor is positioned adjacent to a relatively larger portion of the sides of the second rectangular fin structure and is positioned adjacent to a relatively smaller portion of the sides of the first rectangular fin structure.
摘要翻译：方法和结构包括场效应晶体管结构，其包括位于衬底上的第一矩形翅片结构和第二矩形翅片结构。第二矩形翅片结构的侧面平行于第一矩形翅片结构的侧面。此外，沟槽绝缘体位于基板上并且位于第一矩形翅片结构的一侧和第二矩形鳍结构的一侧之间。栅极导体位于沟槽绝缘体上，位于第一矩形翅片结构的侧面和顶部之上，并且位于第二矩形鳍结构的侧面和顶部之上。栅极导体垂直于第一矩形翅片结构的侧面和第二矩形翅片结构的侧面延伸。此外，栅极绝缘体位于栅极导体和第一矩形翅片结构之间以及栅极导体和第二矩形鳍结构之间。栅极导体定位成与第二矩形鳍结构的相对较大部分的侧面相邻并且被定位成与第一矩形鳍结构的相对较小部分的侧面相邻。

42. 发明授权

US08933490B2 Structure, method and system for complementary strain fill for integrated circuit chips 有权
标题翻译：用于集成电路芯片的互补应变填充的结构，方法和系统
公开(公告)号：US08933490B2
公开(公告)日：2015-01-13
申请号：US13774069
申请日：2013-02-22
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/118 , H01L27/12 , H01L21/8238 , G06F17/50 , H01L21/8234 , H01L27/02 , H01L27/088 , H01L27/092 , H01L21/8228 , H01L21/84
CPC分类号： G06F17/5072 , G06F17/5081 , H01L21/8228 , H01L21/823412 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L27/0922 , H01L27/1203
摘要： A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.
摘要翻译：用于集成电路芯片的互补应变填充的结构，方法和系统。该结构包括具有多个n沟道和p沟道场效应晶体管（FET）的集成电路的第一区域; 第一区域的n沟道场效应晶体管（NFET）上的第一应力层，第一应力类型的第一应力层; 在第一区域的p沟道场效应晶体管（PFET）上的第二应力层，第二应力类型的第二应力层，与第一应力类型相反的第二应力类型; 和所述集成电路的第二区域，所述第二区域不包含FET，所述第二区域包含所述第一应力层的第一子区域和所述第二应力层的第二子区域。

43. 发明申请

US20140353755A1 FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF FORMING SAME 有权
标题翻译：场效应晶体管结构及其形成方法
公开(公告)号：US20140353755A1
公开(公告)日：2014-12-04
申请号：US14457545
申请日：2014-08-12
申请人： International Business Machines Corporation
发明人： Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.
摘要翻译：本公开一般涉及金属氧化物半导体场效应晶体管（MOSFET）结构及其形成方法。 MOSFET结构在衬底上包括至少一个半导体本体; 在所述至少一个半导体主体的顶表面上的电介质盖，其中所述至少一个半导体本体的宽度小于所述电介质盖的宽度; 保护地涂覆所述至少一个半导体主体的栅介质层; 以及栅极电介质层上的至少一个导电栅极。

44. 发明申请

US20140283616A1 WORKFUNCTION MODULATION-BASED SENSOR TO MEASURE PRESSURE AND TEMPERATURE 有权
标题翻译：基于功能调节的传感器来测量压力和温度
公开(公告)号：US20140283616A1
公开(公告)日：2014-09-25
申请号：US13849565
申请日：2013-03-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Balaji Jayaraman , Kota V. R. M. Murali , Edward J. Nowak , Ninad D. Sathaye , Rajesh Sathiyanarayanan
IPC分类号： G01L9/00 , G01K7/01
CPC分类号： G01L9/0042 , G01K7/015 , G01N27/002 , G01N27/4141
摘要： A workfunction modulation-based sensor comprising a field-effect transistor (FET). The FET comprises a substrate, a gate dielectric, a metal gate, a source, a drain, and a layer of sensing material that is electrically connected to the metal gate. An electrical connection that connects to the source of the FET. An electrical connection that connects to the drain of the FET. An electrical connection that connects to the layer of sensing material. An environment that includes an adsorbate gas surrounding, at least a portion of, the layer of sensing material. Wherein the sensing material is adapted to adsorb, at least in part, the adsorbate gas. The amount of adsorbate gas adsorbed on the layer of sensing material modulates the workfunction of the FET such that the degree of adsorbate gas adsorption corresponds to one of the temperature or pressure associated with the environment of the FET.
摘要翻译：一种基于功能调制的传感器，包括场效应晶体管（FET）。 FET包括电连接到金属栅极的衬底，栅极电介质，金属栅极，源极，漏极和感测材料层。连接到FET源极的电气连接。连接到FET的漏极的电气连接。连接到传感材料层的电气连接。环境，其包括围绕传感材料层的至少一部分的被吸附气体。其中感测材料适于至少部分吸附被吸附物质气体。吸附在感应材料层上的吸附气体的量调节FET的功函数，使得吸附气体吸附的程度对应于与FET的环境相关的一个温度或压力。

45. 发明授权

US08809954B2 Partially depleted (PD) semiconductor-on-insulator (SOI) field effect transistor (FET) structure with a gate-to-body tunnel current region for threshold voltage (Vt) lowering and method of forming the structure 有权
标题翻译：部分耗尽（PD）绝缘体上半导体（SOI）场效应晶体管（FET）结构，具有用于阈值电压（Vt）降低的栅 - 体隧道电流区域和形成结构的方法
公开(公告)号：US08809954B2
公开(公告)日：2014-08-19
申请号：US14146869
申请日：2014-01-03
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Andres Bryant , Jiale Liang , Edward J. Nowak
IPC分类号： H01L27/12 , H01L21/00 , H01L21/84
CPC分类号： H01L29/78 , H01L21/26506 , H01L29/32 , H01L29/66477 , H01L29/78612
摘要： Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.
摘要翻译：公开了具有栅对体隧道电流区域（GTBTCR）的场效应晶体管的实施例和方法。在一个实施例中，具有不同导电类型的相邻部分的栅极穿过半导体层的中心部分，以在中心部分内分别在具有不同导电类型的相邻部分之下分别形成沟道区域和GTBTCR。在另一个实施例中，半导体层具有具有沟道区域的中心部分和GTBTCR。 GTBTCR包括：与沟道区相邻并掺杂相同的第一导电类型掺杂剂的较高浓度的第一注入区; 具有第二导电类型的与第一植入区相邻的第二植入区; 以及植入区域之间的增强的生成和重组区域。具有第二导电类型的栅极穿过中心部分。

46. 发明申请

US20140191235A1 MEASURING CURRENT AND RESISTANCE USING COMBINED DIODES/RESISTOR STRUCTURE TO MONITOR INTEGRATED CIRCUIT MANUFACTURING PROCESS VARIATIONS 有权
标题翻译：使用组合二极管/电阻结构测量电流和电阻监视集成电路制造过程变化
公开(公告)号：US20140191235A1
公开(公告)日：2014-07-10
申请号：US14189682
申请日：2014-02-25
申请人： International Business Machines Corporation
发明人： Lyndon R. Logan , Edward J. Nowak , Robert R. Robison , Jonathan K. Winslow
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L23/58 , G01R19/0092 , G01R27/14 , H01L22/30 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.
摘要翻译：使用可操作地连接到计算机化机器的制造设备，在集成电路结构内形成多个二极管/电阻器件。每个二极管/电阻器件包括集成到单个结构中的二极管器件和电阻器件。在使用可操作地连接到计算机化机器的测试设备来测试集成电路结构时测量每个二极管/电阻器件的电阻。在使用测试设备的集成电路结构测试期间，也测量通过每个二极管/电阻器件的电流。然后，根据集成电路结构内的晶体管器件的特性的变化和/或集成电路结构内的晶体管器件的制造工艺的变化来计算电阻和电流的响应曲线。

47. 发明申请

US20140117450A1 PARTIALLY DEPLETED (PD) SEMICONDUCTOR-ON-INSULATOR (SOI) FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH A GATE-TO-BODY TUNNEL CURRENT REGION FOR THRESHOLD VOLTAGE (Vt) LOWERING AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：具有门控电压（Vt）的栅极 - 体积隧道电流区域的局部放电（PD）半导体绝缘体（SOI）场效应晶体管（FET）结构和形成结构的方法
公开(公告)号：US20140117450A1
公开(公告)日：2014-05-01
申请号：US14146869
申请日：2014-01-03
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Andres Bryant , Jiale Liang , Edward J. Nowak
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/78 , H01L21/26506 , H01L29/32 , H01L29/66477 , H01L29/78612
摘要： Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.
摘要翻译：公开了具有栅对体隧道电流区域（GTBTCR）的场效应晶体管的实施例和方法。在一个实施例中，具有不同导电类型的相邻部分的栅极穿过半导体层的中心部分，以在中心部分内分别在具有不同导电类型的相邻部分之下分别形成沟道区域和GTBTCR。在另一个实施例中，半导体层具有具有沟道区域的中心部分和GTBTCR。 GTBTCR包括：与沟道区相邻并掺杂相同的第一导电类型掺杂剂的较高浓度的第一注入区; 具有第二导电类型的与第一植入区相邻的第二植入区; 以及植入区域之间的增强的生成和重组区域。具有第二导电类型的栅极穿过中心部分。

48. 发明申请

US20140061139A1 NANO-FILTER AND METHOD OF FORMING SAME, AND METHOD OF FILTRATION 有权
标题翻译：纳滤器及其形成方法，以及过滤方法
公开(公告)号：US20140061139A1
公开(公告)日：2014-03-06
申请号：US14084139
申请日：2013-11-19
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
IPC分类号： B01D39/20
CPC分类号： B01D39/2082 , B01D2239/025 , B01D2239/0613 , B01D2239/10 , B01D2239/1233 , B82Y30/00
摘要： The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.
摘要翻译：本公开一般涉及纳米过滤器及其形成方法，以及过滤方法。纳米过滤器包括基底和位于入口和出口之间的至少一个纳米线结构。纳米线结构可以包括多个垂直堆叠的水平纳米线。

49. 发明申请

US20130161748A1 STRUCTURE, METHOD AND SYSTEM FOR COMPLEMENTARY STRAIN FILL FOR INTEGRATED CIRCUIT CHIPS 有权
公开(公告)号：US20130161748A1
公开(公告)日：2013-06-27
申请号：US13774069
申请日：2013-02-22
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/12 , G06F17/50
CPC分类号： G06F17/5072 , G06F17/5081 , H01L21/8228 , H01L21/823412 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L27/0922 , H01L27/1203
摘要： A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.

50. 发明申请

US20130043412A1 SERIAL IRRADIATION OF A SUBSTRATE BY MULTIPLE RADIATION SOURCES 有权
标题翻译：通过多个辐射源对衬底的串行辐照
公开(公告)号：US20130043412A1
公开(公告)日：2013-02-21
申请号：US13658861
申请日：2012-10-24
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： G21K5/00
CPC分类号： B23K26/0626 , B23K26/0608 , H01L21/26513 , H01L21/2686
摘要： A system for configuring and utilizing J electromagnetic radiation sources (J≧2) to serially irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I≧2; J≦I) thereon. Pj denotes a normally incident energy flux on each stack from source j. In each of I independent exposure steps, the I stacks are concurrently exposed to radiation from the J sources. Vi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i in exposure step i (i=1, . . . , I). t(i) and Pt(i) are computed such that: Vi is maximal through deployment of source t(i) as compared with deployment of any other source for i=1, . . . , I; and an error E being a function of |V1−S1|, |V2−S2|, . . . , |VI−SI| is about minimized with respect to Pi (i=1, . . . , I).
摘要翻译：一种用于配置和利用J电磁辐射源（J≥2）以串行照射衬底的系统。每个源具有不同的发射辐射的波长和角分布的功能。衬底包括基层和I堆叠（I≥2; J＆lt; I; I）。 Pj表示来自源j的每个堆叠上的正常入射能量通量。在I独立暴露步骤中，I堆叠同时暴露于来自J源的辐射。 Vi和Si分别表示在曝光步骤i（i = 1，...，I）中通过堆叠i传输到衬底中的实际和目标能量通量。计算t（i）和Pt（i），使得：与部署i = 1的任何其他源相比，通过部署源t（i），Vi最大。。。，一世; 并且误差E是| V1-S1 |，| V2-S2 |的函数。。。，| VI-SI | 相对于Pi（i = 1，...，I）被最小化。

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