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41. 发明申请

US20140204677A1 APPARATUSES AND METHODS INCLUDING MEMORY WRITE OPERATION 有权
标题翻译：包括存储器写操作的设备和方法
公开(公告)号：US20140204677A1
公开(公告)日：2014-07-24
申请号：US14222062
申请日：2014-03-21
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3418
摘要： Some embodiments include apparatuses and methods having memory cells and access lines coupled to the memory cells. In one such apparatus, the access lines include a first access line and a second access line. The first access line can be adjacent to the second access line. The memory cells include a memory cell associated with the second access line. A module can be configured to apply a voltage to the first access line during an operation of accessing the memory cell associated with the second access line, and to place the second access line in a floating state during at least a portion of a time interval within the operation. Other embodiments including additional apparatus and methods are described.
摘要翻译：一些实施例包括具有耦合到存储器单元的存储器单元和存取线的装置和方法。在一种这样的装置中，接入线路包括第一接入线路和第二接入线路。第一条接入线可以与第二条接入线相邻。存储器单元包括与第二访问线相关联的存储单元。模块可以被配置为在访问与第二接入线路相关联的存储器单元的操作期间将电压施加到第一接入线路，并且在第二接入线路的时间间隔的至少一部分期间将第二接入线路置于浮置状态的操作。描述包括附加装置和方法的其它实施例。

42. 发明申请

US20140169098A1 APPARATUSES AND METHODS INVOLVING ACCESSING MEMORY CELLS 有权
标题翻译：涉及存取细胞的装置和方法
公开(公告)号：US20140169098A1
公开(公告)日：2014-06-19
申请号：US13718801
申请日：2012-12-18
申请人： MICRON TECHNOLOGY, INC.
发明人： Toru Tanzawa , Satoru Tamada , Koichi Kawai , Tetsuji Manabe
IPC分类号： G11C7/00 , G11C16/06
CPC分类号： G11C8/12 , G11C7/00 , G11C7/18 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C2207/005 , G11C2207/2245
摘要： Apparatuses and methods involving accessing memory cells are described. In one such method, chunks of memory cells in a memory array are enabled to be accessed and then one or more of the chunks are disabled from being accessed. In one such apparatus, an array includes chunks of memory cells and a chunk selector circuit coupled to each chunk to enable the memory cells in the respective chunk to be accessed. Additional embodiments are described.
摘要翻译：描述了涉及访问存储器单元的装置和方法。在一种这样的方法中，可以访问存储器阵列中的存储器单元块，然后禁止一个或多个块被访问。在一种这样的装置中，阵列包括存储器单元的块和耦合到每个块的块选择器电路，以使得可以访问相应块中的存储器单元。描述其他实施例。

43. 发明申请

US20140078827A1 APPARATUSES AND METHODS INCLUDING MEMORY ARRAY AND DATA LINE ARCHITECTURE 有权
标题翻译：包括内存阵列和数据线架构的设备和方法
公开(公告)号：US20140078827A1
公开(公告)日：2014-03-20
申请号：US14089337
申请日：2013-11-25
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： G11C16/04 , G11C16/10
CPC分类号： G11C16/0483 , G11C5/025 , G11C5/06 , G11C16/107 , G11C2213/71 , H01L27/1052 , H01L27/11529 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.
摘要翻译：一些实施例包括具有位于器件的不同器件级别中的存储器单元，位于器件的衬底中的晶体管的至少一部分以及耦合到晶体管和存储器单元的数据线的器件和方法。数据线可以位于晶体管和存储单元之间。描述包括附加装置和方法的其它实施例。

44. 发明授权

US11653497B2 Semiconductor apparatus with multiple tiers, and methods 有权
公开(公告)号：US11653497B2
公开(公告)日：2023-05-16
申请号：US17498503
申请日：2021-10-11
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： H01L21/027 , H01L27/11582 , H01L27/11524 , H01L27/11531 , H01L27/11556 , H01L27/1157 , H01L27/11573 , G11C8/10 , H01L21/02 , H01L27/11529 , H01L29/49
CPC分类号： H01L27/11582 , G11C8/10 , H01L21/02164 , H01L21/02532 , H01L21/02595 , H01L27/1157 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11556 , H01L27/11573 , H01L29/495 , H01L29/4966
摘要： Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

45. 发明申请

US20230015591A1 FIELD EFFECT TRANSISTORS HAVING A FIN 有权
公开(公告)号：US20230015591A1
公开(公告)日：2023-01-19
申请号：US17950556
申请日：2022-09-22
申请人： MICRON TECHNOLOGY, INC.
发明人： Toru Tanzawa
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L27/112
摘要： Methods of forming a transistor might include removing portions of a semiconductor to define a semiconductor fin having an upper portion having an uppermost surface at a first level and extending from the first level to a second level, and a lower portion, wider than the upper portion, having an uppermost surface at the second level and extending from the second level to a third level; forming first and second isolation regions at the third level and adjacent the lower portion of the semiconductor fin; forming a first dielectric overlying portions of the semiconductor that are lower than a level between the first level and the second level; forming a second dielectric overlying an exposed portion of the upper portion of the semiconductor fin; forming a conductor overlying the second dielectric; and forming first and second source/drains in the lower portion of the semiconductor fin at the second level.

46. 发明授权

US11417671B2 Memory device including pass transistors in memory tiers 有权
公开(公告)号：US11417671B2
公开(公告)日：2022-08-16
申请号：US17027399
申请日：2020-09-21
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： G11C16/04 , H01L27/11526 , H01L27/11524 , H01L27/1157 , H01L27/11556 , H01L27/11582 , G11C16/26 , G11C16/10 , H01L27/11573 , H01L27/11575 , G11C8/12 , G11C16/08
摘要： Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. The transistors include sources and drains formed from portions of the semiconductor material. The transistors include gates that are electrically uncoupled to each other.

47. 发明授权

US11201165B2 Memory having memory cell string and coupling components 有权
公开(公告)号：US11201165B2
公开(公告)日：2021-12-14
申请号：US16564967
申请日：2019-09-09
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： H01L27/11582 , H01L27/11556 , H01L23/528 , H01L27/11524 , H01L27/1157 , G11C16/08 , G11C16/10 , G11C5/06 , H04N19/117 , H04N19/14 , H04N19/176 , H04N19/182 , H04N19/61 , H04N19/80 , H04N19/82 , H04N19/86
摘要： Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.

48. 发明授权

US10956642B2 Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information 有权
公开(公告)号：US10956642B2
公开(公告)日：2021-03-23
申请号：US16432632
申请日：2019-06-05
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： G06F30/367 , G11C7/22 , G11C7/10 , G11C13/00 , G11C29/02
摘要： Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line.

49. 发明申请

US20210005624A1 MEMORY ARRAY HAVING CONNECTIONS GOING THROUGH CONTROL GATES 有权
公开(公告)号：US20210005624A1
公开(公告)日：2021-01-07
申请号：US17012297
申请日：2020-09-04
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa , Tamotsu Murakoshi , Deepak Thimmegowda
IPC分类号： H01L27/11556 , H01L29/66 , H01L29/792 , G11C16/04 , H01L27/11529 , H01L27/11548 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L27/11521 , H01L27/11568
摘要： Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.

50. 发明申请

US20200303379A1 THREE-DIMENSIONAL DEVICES HAVING REDUCED CONTACT LENGTH 审中-公开
公开(公告)号：US20200303379A1
公开(公告)日：2020-09-24
申请号：US16890673
申请日：2020-06-02
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： H01L27/108 , H01L27/11531 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L27/11578 , H01L21/74 , H01L27/02 , H01L27/11
摘要： Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.

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