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41. 发明授权

US09601617B2 Fabrication of a transistor including a tunneling layer 有权
公开(公告)号：US09601617B2
公开(公告)日：2017-03-21
申请号：US14604544
申请日：2015-01-23
申请人： QUALCOMM Incorporated
发明人： Jun Yuan , Xia Li , Bin Yang
IPC分类号： H01L29/78 , H01L29/161 , H01L29/66 , H01L29/51 , H01L29/49 , H01L21/28 , H01L29/739
CPC分类号： H01L29/7827 , H01L21/28079 , H01L21/28088 , H01L29/161 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66356 , H01L29/66666 , H01L29/66977 , H01L29/7391
摘要： In a particular embodiment, an apparatus includes an electron tunnel structure. The electron tunnel structure includes a tunneling layer, a channel layer, a source layer, and a drain layer. The tunneling layer and the channel layer are positioned between the source layer and the drain layer. The transistor device further includes a high-k dielectric layer adjacent to the electron tunnel structure.

42. 发明授权

US09236483B2 FinFET with backgate, without punchthrough, and with reduced fin height variation 有权
标题翻译： FinFET带背盖，无穿孔，并具有降低的翅片高度变化
公开(公告)号：US09236483B2
公开(公告)日：2016-01-12
申请号：US14179311
申请日：2014-02-12
申请人： QUALCOMM Incorporated
发明人： Bin Yang , Xia Li , Pr Chidambaram , Choh Fei Yeap
IPC分类号： H01L29/76 , H01L29/94 , H01L29/78 , H01L29/267 , H01L29/06 , H01L29/66 , H03K17/687
CPC分类号： H01L29/7855 , H01L29/0607 , H01L29/267 , H01L29/66795 , H01L29/7842 , H01L29/7848 , H01L29/7851 , H03K17/687 , H03K2017/6878 , H03K2217/0018 , H03K2217/0054
摘要： A FinFET having a backgate and a barrier layer beneath the fin channel of the FinFET, where the barrier layer has a bandgap greater than that of the backgate. The barrier layer serves as an etch stop layer under the fin channel, resulting in reduced fin channel height variation. The backgate provides improved current control. There is less punchthrough due to the higher bandgap barrier layer. The FinFET may also include deeply embedded stressors adjacent to the source/drain diffusions through the high bandgap barrier layer.
摘要翻译：在FinFET的鳍通道下方具有背栅和阻挡层的FinFET，其中阻挡层的带隙大于背栅的带隙。阻挡层在翅片通道下面用作蚀刻停止层，从而减少了翅片通道高度变化。后门提供改进的电流控制。由于较高的带隙阻挡层，穿孔较少。 FinFET还可以包括通过高带隙势垒层与源极/漏极扩散相邻的深埋入的应力源。

43. 发明授权

US09111635B2 Static random access memories (SRAM) with read-preferred cell structures, write drivers, related systems, and methods 有权
标题翻译：具有读优选单元结构的静态随机存取存储器（SRAM），写入驱动器，相关系统和方法
公开(公告)号：US09111635B2
公开(公告)日：2015-08-18
申请号：US13869110
申请日：2013-04-24
申请人： QUALCOMM Incorporated , Industry-Academic Cooperation Foundation, Yonsei University
发明人： Seong-Ook Jung , Younghwi Yang , Bin Yang , Zhongze Wang , Choh fei Yeap
IPC分类号： G11C11/00 , G11C11/412 , G11C11/419
CPC分类号： G11C11/412 , G11C11/417 , G11C11/419 , H01L27/0207 , H01L27/1104 , Y10T29/41
摘要： Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.
摘要翻译：公开了具有读优选单元结构和写驱动器的静态随机存取存储器（SRAM）。在一个实施例中，SRAM具有六个晶体管位单元。读优选位单元通过提供两个反相器来实现，每个反相器具有上拉晶体管，下拉晶体管和通过栅极晶体管。每个上拉晶体管与反馈回路相关联。反馈环路改善了随机的静态噪声容限。每个晶体管具有宽度和长度。传输栅晶体管的长度增加。下拉晶体管的宽度彼此相等，并且也等于通过栅极晶体管的宽度。通过栅极和下拉晶体管的宽度也可以相对于现有设计而增加。也可以使用写辅助电路来提高性能。

44. 发明申请

US20150162405A1 TRANSISTOR WITH A DIFFUSION BARRIER 有权
标题翻译：具有扩散障碍的晶体管
公开(公告)号：US20150162405A1
公开(公告)日：2015-06-11
申请号：US14100760
申请日：2013-12-09
申请人： QUALCOMM Incorporated
发明人： Bin Yang , Xia Li , PR Chidambaram
IPC分类号： H01L29/10 , H01L29/66 , H01L29/205
CPC分类号： H01L29/1045 , H01L21/743 , H01L29/1054 , H01L29/1087 , H01L29/205 , H01L29/66522 , H01L29/66636 , H01L29/66795 , H01L29/7834 , H01L29/7848 , H01L29/785
摘要： An apparatus comprises a substrate. The apparatus also comprises a diffusion barrier formed on a surface of a first region of the substrate. The diffusion barrier is formed using a first material having a first band gap energy. The apparatus further comprises a channel region formed on a surface of the diffusion barrier. The channel region is formed using a second material having a second band gap energy that is lower than the first band gap energy. The apparatus further comprises a back gate contact coupled to the first region of the substrate.
摘要翻译：一种装置包括基板。该装置还包括形成在基板的第一区域的表面上的扩散阻挡层。使用具有第一带隙能量的第一材料形成扩散阻挡层。该装置还包括形成在扩散阻挡层的表面上的沟道区。沟道区域使用具有低于第一带隙能量的第二带隙能量的第二材料形成。该装置还包括耦合到衬底的第一区域的背栅极接触。

45. 发明授权

US09047960B2 Flash memory cell with capacitive coupling between a metal floating gate and a metal control gate 有权
标题翻译：具有金属浮动栅极和金属控制栅极之间的电容耦合的闪存单元
公开(公告)号：US09047960B2
公开(公告)日：2015-06-02
申请号：US13957460
申请日：2013-08-02
申请人： QUALCOMM Incorporated
发明人： Xia Li , Bin Yang , Zhongze Wang
IPC分类号： G11C16/00 , G11C16/10 , H01L21/28 , H01L29/66 , G11C16/14
CPC分类号： G11C16/10 , G11C16/0433 , G11C16/14 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line.
摘要翻译：一种装置包括存储晶体管。存储晶体管包括被配置为存储电荷的浮动栅极和控制栅极。浮动栅极通过电容耦合耦合到控制栅极。浮动门和控制门是金属的。该装置还包括耦合到存储晶体管的存取晶体管。存取晶体管的栅极耦合到字线。存储晶体管和存取晶体管串联耦合在位线和源极线之间。

46. 发明授权

US09012966B2 Capacitor using middle of line (MOL) conductive layers 有权
标题翻译：使用中线（MOL）导电层的电容器
公开(公告)号：US09012966B2
公开(公告)日：2015-04-21
申请号：US13684059
申请日：2012-11-21
申请人： QUALCOMM Incorporated
发明人： PR Chidambaram , Bin Yang
IPC分类号： H01L27/108 , H01L29/94 , H01L49/02 , H01L23/522 , H01L27/06
CPC分类号： H01L27/0629 , H01L23/5223 , H01L23/5228 , H01L28/20 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a metal-insulator-metal (MIM) capacito includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first plate of the MIM capacitor as well as a first set of local interconnects to source and drain regions of a semiconductor device. The method also includes depositing an insulator layer on the first MOL conductive layer as a dielectric layer of the MIM capacitor. The method further includes depositing a second MOL conductive layer on the insulator layer as a second plate of the MIM capacitor.
摘要翻译：一种用于制造金属 - 绝缘体 - 金属（MIM）电容的方法，包括在半导体衬底的浅沟槽隔离（STI）区域上沉积第一中间线（MOL）导电层。第一MOL导电层提供MIM电容器的第一板以及到半导体器件的源极和漏极区域的第一组局部互连。该方法还包括在第一MOL导电层上沉积绝缘体层作为MIM电容器的电介质层。所述方法还包括在所述绝缘体层上沉积作为所述MIM电容器的第二板的第二MOL导电层。

47. 发明申请

US20150069458A1 VERTICAL TUNNEL FIELD EFFECT TRANSISTOR 有权
标题翻译：垂直隧道场效应晶体管
公开(公告)号：US20150069458A1
公开(公告)日：2015-03-12
申请号：US14021795
申请日：2013-09-09
申请人： QUALCOMM Incorporated
发明人： Xia Li , Ming Cai , Bin Yang
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66977 , H01L29/66356 , H01L29/66795 , H01L29/7391 , H01L29/7827
摘要： A tunnel field transistor (TFET) device includes a fin structure that protrudes from a substrate surface. The fin structure includes a base portion proximate to the substrate surface, a top portion, and a first pair of sidewalls extending from the base portion to the top portion. The first pair of sidewalls has a length corresponding to a length of the fin structure. The fin structure also includes a first doped region having a first dopant concentration at the base portion of the fin structure. The fin structure also includes a second doped region having a second dopant concentration at the top portion of the fin structure. The TFET device further includes a gate including a first conductive structure neighboring a first sidewall of the first pair of sidewalls. A dielectric layer electrically isolates the first conductive structure from the first sidewall.
摘要翻译：隧道场晶体管（TFET）器件包括从衬底表面突出的鳍结构。翅片结构包括靠近基底表面的基部，顶部和从基部延伸到顶部的第一对侧壁。第一对侧壁的长度对应于翅片结构的长度。翅片结构还包括在鳍结构的基部处具有第一掺杂剂浓度的第一掺杂区域。鳍结构还包括在鳍结构的顶部具有第二掺杂剂浓度的第二掺杂区。 TFET器件还包括栅极，其包括与第一对侧壁的第一侧壁相邻的第一导电结构。电介质层将第一导电结构与第一侧壁电隔离。

48. 发明授权

US08942034B2 System and method of programming a memory cell 有权
标题翻译：编程存储器单元的系统和方法
公开(公告)号：US08942034B2
公开(公告)日：2015-01-27
申请号：US13759344
申请日：2013-02-05
申请人： QUALCOMM Incorporated
发明人： Xia Li , Bin Yang
IPC分类号： G11C16/04 , G11C5/06 , G11C7/12 , G06F17/50 , G11C11/40 , G11C17/16 , G11C11/404 , G11C5/14
CPC分类号： G11C17/18 , G06F17/5045 , G11C5/06 , G11C5/146 , G11C7/12 , G11C11/40 , G11C11/404 , G11C11/5692 , G11C16/04 , G11C17/16 , G11C2211/4016
摘要： A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate.
摘要翻译：一种方法包括在半导体晶体管结构中选择性地产生第一击穿条件和第二击穿条件。第一击穿条件在半导体晶体管结构的源极重叠区域和半导体晶体管结构的栅极之间。第二击穿条件是在半导体晶体管结构的覆盖区域和栅极之间。

49. 发明申请

US20140264610A1 METAL OXIDE SEMICONDUCTOR (MOS) ISOLATION SCHEMES WITH CONTINUOUS ACTIVE AREAS SEPARATED BY DUMMY GATES AND RELATED METHODS 有权
标题翻译：具有连续活性区域的金属氧化物半导体（MOS）隔离方案，由DUYY GATES和相关方法分离
公开(公告)号：US20140264610A1
公开(公告)日：2014-09-18
申请号：US13799955
申请日：2013-03-13
申请人： QUALCOMM INCORPORATED
发明人： Bin Yang , Xia Li , PR Chidambaram
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/6681 , H01L21/7624 , H01L21/765 , H01L21/823842 , H01L21/823878 , H01L27/0207 , H01L29/785
摘要： Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.
摘要翻译：在详细描述中公开的实施例包括具有由伪栅极分开的连续有效区域的金属氧化物半导体（MOS）隔离方案。 MOS器件包括由具有作为n金属或p金属的功函数的材料形成的有源区域。使用具有类似功函数的材料在该有效区域上形成活性组分。通过在有源部件之间定位一个虚拟栅极来实现隔离。虚拟门由相对于有源区的材料具有相反功函数的材料制成。例如，如果有源区域是p金属材料，则虚拟栅极将由n金属制成，反之亦然。

50. 发明授权

US08836079B2 Metal-on-metal (MoM) capacitors having laterally displaced layers, and related systems and methods 有权
标题翻译：具有横向位移层的金属对金属（MoM）电容器，以及相关的系统和方法
公开(公告)号：US08836079B2
公开(公告)日：2014-09-16
申请号：US13748768
申请日：2013-01-24
申请人： QUALCOMM Incorporated
发明人： Xia Li , Bin Yang
IPC分类号： H01L21/02
CPC分类号： H01L28/60 , H01L23/5223 , H01L28/88 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Metal-on-Metal (MoM) capacitors having laterally displaced layers and related systems and methods are disclosed. In one embodiment, a MoM capacitor includes a plurality of vertically stacked layers that are laterally displaced relative to one another. Lateral displacement of the layers minimizes cumulative surface process variations making a more reliable and uniform capacitor.
摘要翻译：公开了具有横向移位层的金属对金属（MoM）电容器及相关系统和方法。在一个实施例中，MoM电容器包括相对于彼此横向移位的多个垂直堆叠的层。层的横向位移最小化累积的表面处理变化，从而形成更可靠和更均匀的电容器。

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