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41. 发明申请

US20140349236A1 Method for Forming Semiconductor Structure Having Opening 有权
标题翻译：形成具有开口的半导体结构的方法
公开(公告)号：US20140349236A1
公开(公告)日：2014-11-27
申请号：US13899577
申请日：2013-05-22
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chieh-Te Chen , Yu-Tsung Lai , Hsuan-Hsu Chen , Feng-Yi Chang
IPC分类号： G03F7/22
CPC分类号： H01L21/28 , H01L21/0332 , H01L21/31144 , H01L21/76816
摘要： A method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. A pattern density of the first region is substantially greater than that of the second region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only.
摘要翻译：提供一种形成具有开口的半导体结构的方法。首先，提供衬底，其中在衬底上限定第一区域和第二区域，并且将第一区域和第二区域的重叠区域定义为第三区域。第一区域的图案密度基本上大于第二区域的图案密度。然后，在基板上形成材料层。第一硬掩模和第二硬掩模形成在材料层上。第一区域中的第一硬掩模被去除以形成图案化的第一硬掩模。去除第三区域中的第二硬掩模以形成图案化的第二硬掩模。最后，通过使用图案化的第二硬掩模层作为掩模来对材料层进行图案化，以仅在第三区域中形成至少一个开口。

42. 发明申请

US20140315365A1 METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20140315365A1
公开(公告)日：2014-10-23
申请号：US13866456
申请日：2013-04-19
申请人： UNITED MICROELECTRONICS CORP.
发明人： Li-Chiang Chen , Jiunn-Hsiung Liao , Hsuan-Hsu Chen , Feng-Yi Chang , Chieh-Te Chen , Shang-Yuan Tsai , Ching-Pin Hsu
IPC分类号： H01L29/423 , H01L29/66
CPC分类号： H01L29/42372 , H01L21/28088 , H01L21/32134 , H01L21/32135 , H01L21/823828 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.
摘要翻译：提供一种形成半导体器件的方法。在基板上形成包括虚拟栅极的至少一个栅极结构。形成接触蚀刻停止层和电介质层以覆盖栅极结构。接触蚀刻停止层的一部分和电介质层的一部分被去除以暴露栅极结构的顶部。执行干蚀刻处理以去除栅极结构的虚拟栅极的一部分。对剩余的虚拟栅极的表面进行氢化处理。执行湿蚀刻处理以去除剩余的虚拟栅极，从而形成栅极沟槽。

43. 发明授权

US08785283B2 Method for forming semiconductor structure having metal connection 有权
标题翻译：用于形成具有金属连接的半导体结构的方法
公开(公告)号：US08785283B2
公开(公告)日：2014-07-22
申请号：US13705183
申请日：2012-12-05
申请人： United Microelectronics Corp.
发明人： Chieh-Te Chen , Feng-Yi Chang , Chih-Sen Huang , Ching-Wen Hung , Ching-Pin Hsu
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L21/76816 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L29/66628 , H01L29/66636 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.
摘要翻译：本发明提供一种形成具有金属连接的半导体结构的方法。提供衬底，并在其上形成晶体管和第一ILD层。第一接触插塞形成在第一ILD层中以电连接源极/漏极区域。在第一ILD层上形成第二ILD层和第三ILD层。形成在栅极上方的第一开口和在第一接触插塞上方的第二开口，其中第一接触插塞的深度比第二开口的深度深。接下来，加深第一开口和第二开口。最后，将金属层填充到第一开口和第二开口中，以分别形成第一金属连接和第二金属连接。

44. 发明申请

US20210193665A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20210193665A1
公开(公告)日：2021-06-24
申请号：US17191712
申请日：2021-03-04
申请人： UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
发明人： Chien-Ming Lu , Fu-Che Lee , Feng-Yi Chang
IPC分类号： H01L27/108
摘要： A semiconductor memory device includes a substrate, a dielectric layer, plural bit lines, at least one bit line contact, a spacer structure and a spacer layer. The substrate has an isolation area to define plural active areas. The dielectric layer is disposed on the substrate, and the dielectric layer includes a bottom layer having a sidewall being retracted from sidewalls of other layers of the dielectric layer. The plural bit lines are disposed on the dielectric stacked structure, along a direction, and the at least one bit line contact is disposed below one of the bit lines, within the substrate. The spacer structure is disposed at sidewalls of each of the bit lines, and the spacer layer is disposed on the spacer structure to directly in contact with the spacer structure and the other layers of the dielectric layer.

45. 发明授权

US10854613B2 Buried word line of a dynamic random access memory and method for fabricating the same 有权
公开(公告)号：US10854613B2
公开(公告)日：2020-12-01
申请号：US16406017
申请日：2019-05-08
申请人： UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
发明人： Feng-Yi Chang , Chun-Hsien Lin , Fu-Che Lee
IPC分类号： H01L27/108 , H01L29/423 , H01L29/49 , H01L21/02 , H01L29/51 , H01L29/06
摘要： A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.

46. 发明授权

US10825818B2 Method of forming semiconductor device 有权
公开(公告)号：US10825818B2
公开(公告)日：2020-11-03
申请号：US16211239
申请日：2018-12-06
申请人： UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
发明人： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC分类号： H01L27/108 , H01L21/768
摘要： A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping layer. The bit lines are disposed on a substrate within a cell region thereof, and the transistor is disposed on the substrate within a periphery region. The plugs are disposed in the dielectric layer, within the cell region and the periphery region respectively. The capping layer is disposed on the dielectric layer, and the capping layer disposed within the periphery region is between those plugs. That is, a portion of the dielectric layer is therefore between the capping layer and the transistor.

47. 发明授权

US10734284B2 Method of self-aligned double patterning 有权
公开(公告)号：US10734284B2
公开(公告)日：2020-08-04
申请号：US16134976
申请日：2018-09-19
申请人： UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
发明人： Feng-Yi Chang , Fu-Che Lee , Ying-Chih Lin , Gang-Yi Lin , Chieh-Te Chen , Yi-Ching Chang
IPC分类号： H01L21/033 , H01L21/768 , H01L21/308 , H01L21/28 , H01L21/3213 , H01L21/311
摘要： A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.

48. 发明授权

US10714480B2 Method for fabricating contact plug in dynamic random access memory 有权
公开(公告)号：US10714480B2
公开(公告)日：2020-07-14
申请号：US16172845
申请日：2018-10-28
申请人： UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
发明人： Feng-Yi Chang , Fu-Che Lee
IPC分类号： H01L27/108 , H01L23/535
摘要： A method for fabricating a semiconductor device includes the following steps. First, a contact structure is formed in the insulating layer. Preferably, the contact structure includes a bottom portion in part of the insulating layer and a top portion on part of the bottom portion and extending to cover part of the insulating layer. Next, a dielectric layer is formed on the bottom portion and the top portion, part of the dielectric layer is removed to form a first opening exposing part of the top portion and part of the bottom portion, and a capacitor is formed in the first opening and contacting the pad portion and the contact portion directly.

49. 发明授权

US10700071B1 Method for forming semiconductor pattern 有权
公开(公告)号：US10700071B1
公开(公告)日：2020-06-30
申请号：US16258657
申请日：2019-01-27
申请人： UNITED MICROELECTRONICS CORP.
发明人： Gang-Yi Lin , Shih-Fang Tzou , Fu-Che Lee , Feng-Yi Chang , Ying-Chih Lin , Kai-Lou Huang , Yi-Ching Chang
IPC分类号： H01L21/033 , H01L21/308 , H01L27/108
摘要： The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.

50. 发明授权

US10658366B2 Semiconductor device and method for fabricating the same 有权
公开(公告)号：US10658366B2
公开(公告)日：2020-05-19
申请号：US15920468
申请日：2018-03-14
申请人： UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
发明人： Chia-Liang Liao , Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen , Yi-Wang Zhan
IPC分类号： H01L27/108 , H01L21/768 , H01L23/535 , H01L21/311 , H01L23/532 , H01L23/522
摘要： A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.

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