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41. 发明申请

US20210182357A1 SYSTEM AND METHOD FOR MODEL PARAMETER OPTIMIZATION 有权
公开(公告)号：US20210182357A1
公开(公告)日：2021-06-17
申请号：US16714347
申请日：2019-12-13
申请人： Cray Inc.
发明人： Samuel H. Partee , Benjamin J. Robbins , Michael F. Ringenburg
IPC分类号： G06F17/12 , G06N20/20 , G06F17/13
摘要： One embodiment can provide a method and system for tuning parameters of a numerical model of a physical system. During operation, the system can obtain, using a machine-learning technique, a parameter-transform model for mapping parameters of the numerical model at a first resolution to parameters of the numerical model at a second resolution, the second resolution being higher than the first resolution. The system can perform a parameter-tuning operation on the numerical model at a first resolution to obtain a first set of tuned parameters and apply the parameter-transform model on the first set of tuned parameters to obtain a second set of tuned parameters at a second resolution. The system can then generate behavior information associated with the physical system by running the numerical model at the second resolution using the second set of tuned parameters.

42. 发明授权

US10966311B2 Method for cross-talk reduction technique with fine pitch vias 有权
公开(公告)号：US10966311B2
公开(公告)日：2021-03-30
申请号：US16882146
申请日：2020-05-22
申请人： CRAY INC.
发明人： Hyunjun Kim , Andrew J. Becker , Paul Taylor Wildes
IPC分类号： H05K1/02 , H05K1/11 , H05K3/00 , H05K3/40 , H05K1/18 , H05K1/14 , H05K3/42
摘要： Systems and methods are provided for reducing crosstalk between differential signals in a printed circuit board (PCB) using fine pitch vias. A pair of contact pads are on the top surface of the PCB and configured to couple a PCB component to the PCB, the contacts a first distance from each other. A first via of a plurality of vias is electrically coupled to a first contact of the pair of contacts and a second via is electrically coupled to a second contact, the first via and second via a second distance from each other, the second distance being less than current standards for minimum via pitch. Each via comprises a via pad on the top surface and a plated through-hole extending from the top surface to a termination point. A separator gap is between the first via and the second via.

43. 发明授权

US10554519B2 System and method for dampening power swings in distributed computer environments 有权
公开(公告)号：US10554519B2
公开(公告)日：2020-02-04
申请号：US15018823
申请日：2016-02-08
申请人： Cray Inc.
发明人： Matthew Kappel , David Rush , Steve Martin , Jim Robanske
IPC分类号： H04L12/26
摘要： In a large scale computing system, a supervisory system is utilized to monitor the operations and requests of multiple components, and to manage such requests so that overall power considerations for the entire system are considered. The supervisory system has the ability to identify requests and aggregations of simultaneous requests that will create an adverse power effect, and to apply overall control methodologies which will help to minimize these adverse effects.

44. 发明授权

US10034416B2 Transverse cooling system and method 有权
公开(公告)号：US10034416B2
公开(公告)日：2018-07-24
申请号：US14887275
申请日：2015-10-19
申请人： Cray Inc.
发明人： Gregory W. Pautsch , Eric D. Lakin
IPC分类号： H05K7/20
摘要： A system and method for cooling a plurality of electronics cabinets having horizontally positioned electronics assemblies. The system includes at least one blower configured to direct air horizontally across the electronics assemblies, and at least one intercooler configured to extract heat from the air flow such that the system is room neutral, meaning that the ambient temperature remains constant during operation of the system. A plurality of chassis backplanes and power supplies may also include an intercooler, wherein the intercoolers are electronically controlled such that the system is room neutral.

45. 发明授权

US09946654B2 High-bandwidth prefetcher for high-bandwidth memory 有权
公开(公告)号：US09946654B2
公开(公告)日：2018-04-17
申请号：US15335041
申请日：2016-10-26
申请人： Cray Inc.
发明人： Sanyam Mehta , James Robert Kohn , Daniel Jonathan Ernst , Heidi Lynn Poxon , Luiz DeRose
IPC分类号： G06F12/00 , G06F12/0862 , G06F12/1045
CPC分类号： G06F12/0862 , G06F12/1054 , G06F2212/602 , G06F2212/68
摘要： A method for prefetching data into a cache is provided. The method allocates an outstanding request buffer (“ORB”). The method stores in an address field of the ORB an address and a number of blocks. The method issues prefetch requests for a degree number of blocks starting at the address. When a prefetch response is received for all the prefetch requests, the method adjusts the address of the next block to prefetch and adjusts the number of blocks remaining to be retrieved and then issues prefetch requests for a degree number of blocks starting at the adjusted address. The prefetching pauses when a maximum distance between the reads of the prefetched blocks and the last prefetched block is reached. When a read request for a prefetched block is received, the method resumes prefetching when a resume criterion is satisfied.

46. 发明授权

US09674091B2 Congestion causation in a network interconnect 有权
公开(公告)号：US09674091B2
公开(公告)日：2017-06-06
申请号：US15169986
申请日：2016-06-01
申请人： Cray Inc.
发明人： Laurence S. Kaplan , Edwin Lloyd Froese , Christopher Brian Johns , Matthew Paul Kelly , Aaron Forest Godfrey , Brent Thomas Shields
IPC分类号： H04L12/801 , G06F15/173 , H04L12/26 , H04L29/08 , H04L12/24
CPC分类号： H04L47/12 , G06F15/17312 , H04L41/0677 , H04L43/0852 , H04L43/0882 , H04L43/0894 , H04L47/11 , H04L67/10
摘要： A method and system for detecting congestion in a network of nodes, abating the network congestion, and identifying the cause of the network congestion is provided. A congestion detection system may comprise a detection system, an abatement system, and a causation system. The detection system monitors the performance of network components such as the network interface controllers and tiles of routers to determine whether the network is congested such that a delay in delivering packets becomes unacceptable. Upon detecting that the network is congested, an abatement system abates the congestion by limiting the rate at which packets are injected into the network from the nodes. Upon detecting that the network is congested, a causation system may identify the job that is executing on a node that is the cause of the network congestion.

47. 发明授权

US09310856B2 Computer cabinets having progressive air velocity cooling systems and associated methods of manufacture and use 有权
公开(公告)号：US09310856B2
公开(公告)日：2016-04-12
申请号：US13864423
申请日：2013-04-17
申请人： Cray Inc.
发明人： Wade J. Doll
IPC分类号： H05K7/20 , G06F1/20
CPC分类号： G06F1/20 , H05K7/20736
摘要： Computer cabinets, such as supercomputer cabinets, having progressive air velocity cooling systems are described herein. In one embodiment, a computer cabinet includes an air mover positioned beneath a plurality of computer module compartments. The computer module compartments can be arranged in tiers with the computer modules in each successive tier being positioned closer together than the computer modules in the tier directly below. The computer cabinet can also include one or more shrouds, flow restrictors, and/or sidewalls that further control the direction and/or speed of the cooling air flow through the cabinet.

48. 发明授权

US09160607B1 Method and apparatus for deadlock avoidance 有权
标题翻译：防止死锁的方法和装置
公开(公告)号：US09160607B1
公开(公告)日：2015-10-13
申请号：US13798074
申请日：2013-03-12
申请人： Cray Inc.
发明人： Edwin L. Froese , Eric P. Lundberg , Igor Gorodetsky , Howard Pritchard , Charles Giefer , Robert L. Alverson , Duncan Roweth
IPC分类号： G06F15/167 , H04L29/08 , G06F9/45 , G06F9/52 , G06F9/54 , G06F15/00 , G06F9/46
CPC分类号： H04L67/10 , G06F8/458 , G06F9/52 , G06F9/524 , G06F9/54 , G06F15/167 , H04L12/2602 , H04L43/00 , H04L43/02 , H04L45/02 , H04L45/04 , H04L67/2842
摘要： An improved method for the prevention of deadlock in a massively parallel processor (MPP) system wherein, prior to a process sending messages to another process running on a remote processor, the process allocates space in a deadlock-avoidance FIFO. The allocated space provides a “landing zone” for requests that the software process (the application software) will subsequently issue using a remote-memory-access function. In some embodiments, the deadlock-avoidance (DLA) function provides two different deadlock-avoidance schemes: controlled discard and persistent reservation. In some embodiments, the software process determines which scheme will be used at the time the space is allocated.
摘要翻译：一种用于在大规模并行处理器（MPP）系统中防止死锁的改进方法，其中在将消息发送到在远程处理器上运行的另一进程之前，该进程在死锁避免FIFO中分配空间。分配的空间为软件进程（应用软件）随后将使用远程存储器访问功能发出的请求提供“着陆区域”。在一些实施例中，死锁避免（DLA）功能提供两种不同的死锁避免方案：受控丢弃和永久保留。在一些实施例中，软件过程确定在分配空间时将使用哪种方案。

49. 发明授权

US09154400B2 Dynamically updating routing information while avoiding deadlocks and preserving packet order after a configuration change 有权
标题翻译：动态更新路由信息，同时避免死锁，并在配置更改后保留数据包顺序
公开(公告)号：US09154400B2
公开(公告)日：2015-10-06
申请号：US13104799
申请日：2011-05-10
申请人： Aaron F. Godfrey , Christopher B. Johns
发明人： Aaron F. Godfrey , Christopher B. Johns
IPC分类号： G06F15/177 , H04L12/751 , H04L12/703
CPC分类号： H04L45/02 , H04L45/28
摘要： A system for allowing dynamic changing of routing information of a network interconnect while avoiding deadlocks and preserving packet ordering. A network resiliency system detects when an error in the network interconnect occurs and dynamically generates new routing information for the routers that factors in the detected error. The network resiliency system then generates new routing information that factors in the failure. The network resiliency system then directs the network interconnect to enter a quiescent state in which no packets are transiting through the network interconnect. After the network interconnect enters the quiescent state, the network resiliency system directs the loading of the new routing information into the routing tables of the network interconnect and then directs the network interconnect to start injecting request packets into the network interconnect.
摘要翻译：一种用于允许动态改变网络互连的路由信息同时避免死锁并保持分组排序的系统。网络弹性系统检测何时发生网络互连中的错误，并动态地为导致检测到的错误的路由器生成新的路由信息。网络弹性系统然后生成导致故障的新路由信息。然后，网络弹性系统引导网络互连进入其中没有分组正在通过网络互连转移的静止状态。网络互连进入静态后，网络弹性系统将新的路由信息的载入指向网络互连的路由表，然后引导网络互连开始向网络互连注入请求报文。

50. 发明授权

US08924654B1 Multistreamed processor vector packing method and apparatus 有权
标题翻译：多流处理器向量包装方法和装置
公开(公告)号：US08924654B1
公开(公告)日：2014-12-30
申请号：US10643744
申请日：2003-08-18
申请人： Vincent J. Graziano , James R. Kohn
发明人： Vincent J. Graziano , James R. Kohn
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/52 , G06F15/17325 , G06F15/8053
摘要： A computerized method, apparatus, and executable instructions on a machine readable medium for using multiple processors in parallel to create a pack vector from an array in memory. In some embodiments creating the pack vector includes reading portions of the array into a plurality of processors that each select a subset of elements from the their respective portions of the array based on a predetermined criteria. Some embodiments further include counting each of the selected subsets of elements and storing each count in a commonly accessible storage location, reading into the processors at least some of the count values once all of the processors have stored their count, and storing only the selected subsets of elements in the pack vector based at least in part on the count values.
摘要翻译：在机器可读介质上的计算机化方法，装置和可执行指令，用于并行地使用多个处理器以从存储器中的阵列创建包向量。在创建包向量的一些实施例中，包括将阵列的部分读入多个处理器，每个处理器基于预定标准从阵列的各自部分中选择元素的子集。一些实施例还包括对所选择的元件子集中的每一个进行计数，并将每个计数存储在共同可访问的存储位置中，一旦所有处理器都存储了它们的计数，就将至少一些计数值读入处理器，并且仅存储所选择的子集至少部分地基于计数值来实现包向量中的元素。

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