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41. 发明授权

US11386941B1 Signal receiver with skew-tolerant strobe gating 有权
公开(公告)号：US11386941B1
公开(公告)日：2022-07-12
申请号：US17117411
申请日：2020-12-10
申请人： Rambus Inc.
发明人： Neeraj Purohit , Navin Kumar Mishra , Anirudha Shelke
IPC分类号： H03K5/135 , G11C7/22 , G11C7/10
摘要： A gating signal for masking overhead transitions in a data-strobe signal is generated adaptively based on timing events in the incoming data-strobe signal itself to yield a gating window that opens and closes deterministically with respect to active edges of the data-strobe signal.

42. 发明授权

US11379136B2 Adjustable access energy and access latency memory system and devices 有权
公开(公告)号：US11379136B2
公开(公告)日：2022-07-05
申请号：US17075357
申请日：2020-10-20
申请人： Rambus Inc.
发明人： Frederick A. Ware , John Eric Linstadt
IPC分类号： G06F3/06 , G11C11/4091 , G11C11/4076 , G11C7/06 , G11C7/22 , G11C7/18 , G11C11/4097
摘要： Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

43. 发明申请

US20220209999A1 HIGH SPEED SIGNALING SYSTEM WITH ADAPTIVE TRANSMIT PRE-EMPHASIS 有权
公开(公告)号：US20220209999A1
公开(公告)日：2022-06-30
申请号：US17573471
申请日：2022-01-11
申请人： Rambus Inc.
发明人： Vladimir M. Stojanovic , Andrew C. Ho , Anthony Bessios , Fred F. Chen , Elad Alon , Mark A. Horowitz
IPC分类号： H04L25/49 , H04L25/02 , H04L25/03 , H04L25/06 , H04B1/04
摘要： A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

44. 发明申请

US20220208267A1 MEMORY MODULE FOR PLATFORM WITH NON-VOLATILE STORAGE 有权
公开(公告)号：US20220208267A1
公开(公告)日：2022-06-30
申请号：US17573456
申请日：2022-01-11
申请人： Rambus Inc.
发明人： Aws Shallal , Nigel Alvares , Sarvagya Kochak
IPC分类号： G11C14/00 , G06F12/0804
摘要： A system that includes a non-volatile memory subsystem having non-volatile memory. The system also includes a plurality of memory modules that are separate from the non-volatile memory subsystem. Each memory module can include a plurality of random access memory packages where each first random access memory package includes a primary data port and a backup data port. Each memory module can include a storage interface circuit coupled to the backup data ports of the random access memory packages. The storage interface circuit offloads data from the memory module in the event of a power loss by receiving data from the backup data ports of the random access memory packages and transmitting the data to the non-volatile memory subsystem.

45. 发明授权

US11372784B2 Calibration protocol for command and address bus voltage reference in low-swing single-ended signaling 有权
公开(公告)号：US11372784B2
公开(公告)日：2022-06-28
申请号：US16709506
申请日：2019-12-10
申请人： Rambus Inc.
发明人： Pravin Kumar Venkatesan , Liji Gopalakrishnan , Kashinath Ullhas Prabhu , Makarand Ajit Shirasgaonkar
IPC分类号： G06F13/16
摘要： A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

46. 发明授权

US11372147B2 Phase gratings with odd symmetry for high-resolution lensless optical sensing 有权
公开(公告)号：US11372147B2
公开(公告)日：2022-06-28
申请号：US17245320
申请日：2021-04-30
申请人： Rambus Inc.
发明人： Patrick R. Gill , David G. Stork
IPC分类号： G02B5/30 , G02B5/18 , G02B27/46 , H04N5/335 , H01L27/146 , G02B27/42 , H04N5/232
摘要： Image-sensing devices include odd-symmetry gratings that cast interference patterns over a photodetector array. Grating features offer considerable insensitivity to the wavelength of incident light, and to the manufactured distance between the grating and the photodetector array. Photographs and other image information can be extracted from interference patterns captured by the photodetector array. Images can be captured without a lens, and cameras can be made smaller than those that are reliant on lenses and ray-optical focusing.

47. 发明申请

US20220199132A1 LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST 有权
公开(公告)号：US20220199132A1
公开(公告)日：2022-06-23
申请号：US17432064
申请日：2020-02-25
申请人： Rambus Inc.
发明人： Torsten Partsch
IPC分类号： G11C7/22
摘要： In a memory component having a command/address interface, timing interface and data interface, the command/address interface receives a first command/address value from a control component during a first interval and a second command/address value from the control component during a second interval. The timing interface receives a data strobe from the control component during the first interval and a data clock from the control component during the second interval, the data strobe departing from a parked voltage level to commence toggling at a time corresponding to reception of the first command/address value, and the data clock toggling throughout the second interval regardless of second command/address value reception-time. The data interface samples first write data corresponding to the first command/address value at times indicated by toggling of the data strobe, and samples second write data corresponding to the second command/address value at times indicated by toggling of the data clock.

48. 发明申请

US20220190846A1 SINGLE ERROR CORRECT DOUBLE ERROR DETECT (SECDED) ERROR CODING WITH BURST ERROR DETECTION CAPABILITY 有权
公开(公告)号：US20220190846A1
公开(公告)日：2022-06-16
申请号：US17548176
申请日：2021-12-10
申请人： Rambus Inc.
发明人： Michael Thomas Imel
IPC分类号： H03M13/11 , H03M13/19
摘要： An integrated circuit (IC) device is disclosed. The IC device includes an error encoder to receive a word of k bits and to encode the word using a G-matrix to generate an encoded word of n bits. The n bits include the k bits and n-k check bits. The G matrix is based on a parity check matrix defining a single error correct, double error detect, and burst error detect (SECDEDBED) code. An error decoder receives the encoded word and applies the parity check matrix to the encoded word. The parity check matrix is configured to generate a syndrome from the encoded word. The syndrome being used to detect a random double bit error, a random single bit error, and a burst error of between two and m bits within m adjacent bits of an m-bit subset of the data word starting from an m-bit boundary of the word of k bits, and where m

49. 发明申请

US20220188249A1 MEMORY APPLIANCE COUPLINGS AND OPERATIONS 有权
公开(公告)号：US20220188249A1
公开(公告)日：2022-06-16
申请号：US17556376
申请日：2021-12-20
申请人： Rambus Inc.
发明人： Vlad Fruchter , Keith Lowery , George Michael Uhler , Steven Woo , Chi-Ming (Philip) Yeung , Ronald Lee
IPC分类号： G06F13/16 , G06F13/40 , G06F13/42
摘要： System and method for improved transferring of data involving memory device systems. A memory appliance (MA) comprising a plurality of memory modules is configured to store data within the plurality of memory modules and further configured to receive data commands from the first server and a second server coupled to the MA. The data commands may include direction memory access commands such that the MA can service the data commands while bypassing a host controller of the MA.

50. 发明授权

US11361839B2 Command/address channel error detection 有权
公开(公告)号：US11361839B2
公开(公告)日：2022-06-14
申请号：US17049282
申请日：2019-03-20
申请人： Rambus Inc.
发明人： John Eric Linstadt , Frederick A. Ware
IPC分类号： G11C29/42 , G11C8/18 , G11C29/18 , G11C29/44
摘要： A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.

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