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41. 发明授权

US10367132B2 Nanoscale device comprising an elongated crystalline nanostructure 有权
公开(公告)号：US10367132B2
公开(公告)日：2019-07-30
申请号：US15322701
申请日：2015-07-02
申请人： University of Copenhagen
发明人： Peter Krogstrup , Thomas Sand Jespersen , Charles M. Marcus , Jesper Nygård
IPC分类号： H01L39/24 , H01L39/02 , B82Y10/00 , B82Y40/00 , H01L29/43 , H01L29/66 , H01L29/06 , H01L29/41 , H01L39/22 , H01L39/12 , C23C14/28 , C30B11/12 , C30B23/02 , C30B23/06 , C30B29/62
摘要： The present disclosure relates to nanoscale device comprising an elongated crystalline nanostructure, such as a nanowire crystal, a nanowhisker crystal or a nanorod crystal, and a method for producing thereof. One embodiment relates to a nanoscale device comprising an elongated crystalline semiconductor nanostructure, such as a nanowire (crystal) or nanowhisker (crystal) or nanorod (crystal), having a plurality of substantially plane side facets, a crystalline structured first facet layer of a superconductor material covering at least a part of one or more of said side facets, and a second facet layer of a superconductor material covering at least a part of the first facet layer, the superconductor material of the second facet layer being different from the superconductor material of the first facet layer, wherein the crystalline structure of the semiconductor nanostructure is epitaxially matched with the crystalline structure of the first facet layer on the interface between the two crystalline structures.

42. 发明授权

US10361159B2 Semiconductor device having contacts with varying widths 有权
公开(公告)号：US10361159B2
公开(公告)日：2019-07-23
申请号：US15820509
申请日：2017-11-22
申请人： Samsung Electronics Co., Ltd.
发明人： Jong Ho You , Sang Young Kim , Byung Chan Ryu
IPC分类号： H01L21/76 , H01L21/82 , H01L29/41 , H01L29/66 , H01L29/78 , H01L23/528 , H01L23/522 , H01L29/417 , H01L21/768 , H01L29/45 , H01L21/8234 , H01L23/532
摘要： A semiconductor device includes a substrate having a plurality of fins protruding therefrom and an active region on the fins. The device further includes a contact including a conductive region having a concave portion defining an upper portion and a lower portion of the conductive region, an interlayer insulating layer on the active region, and a side insulating layer interposed between the interlayer insulating layer and the lower portion of the conductive region.

43. 发明申请

US20190181010A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20190181010A1
公开(公告)日：2019-06-13
申请号：US15754951
申请日：2016-08-23
申请人： HOSEI UNIVERSITY , SCIOCS COMPANY LIMITED , SUMITOMO CHEMICAL COMPANY, LIMITED
发明人： Tohru NAKAMURA , Tomoyoshi MISHIMA , Hiroshi OHTA , Yasuhiro YAMAMOTO , Fumimasa HORIKIRI
IPC分类号： H01L21/283 , H01L29/06 , H01L29/41 , H01L29/868
摘要： A semiconductor device includes a semiconductor member having a mesa structure in which a first semiconductor layer and a second semiconductor layer are laminated on each other and having a pn junction; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode connected to the first semiconductor layer on a lower surface of the first semiconductor layer, and having a capacitance of the insulating film when a reverse bias voltage is applied between the first electrode and the second electrode, so that a first voltage applied to the insulating film between a corner position (a first position) where the side surface of the insulating film disposed on the side surface of the mesa structure and the upper surface of the insulating film disposed on the outside upper surface of the mesa structure are connected to each other, and a corner position (a second position) where the side surface of the mesa structure and the outside upper surface of the mesa structure are connected to each other, is equal to or smaller than a second voltage applied to the first semiconductor layer between a pn junction interface (a third position) in a lower part of a region where the first electrode is in contact with the second semiconductor layer, and a position directly under the third position (a fourth position) at a height of the second position.

44. 发明授权

US10276718B2 FinFET having a relaxation prevention anchor 有权
公开(公告)号：US10276718B2
公开(公告)日：2019-04-30
申请号：US15692721
申请日：2017-08-31
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Sheng-Hsiung Wang , Yung Feng Chang , Tung-Heng Hsieh
IPC分类号： H01L29/66 , H01L29/78 , H01L29/41 , H01L27/08 , H01L27/12 , H01L21/82 , H01L21/84 , H01L21/8238 , H01L27/092
摘要： A method and structure for mitigating strain loss (e.g., in a FinFET channel) includes providing a semiconductor device having a substrate having a substrate fin portion, an active fin region formed over a first part of the substrate fin portion, a pickup region formed over a second part of the substrate fin portion, and an anchor formed over a third part of the substrate fin portion. In some embodiments, the substrate fin portion includes a first material, and the active fin region includes a second material different than the first material. In various examples, the anchor is disposed between and adjacent to each of the active fin region and the pickup region.

45. 发明授权

US10244637B2 Composite transparent conductors and methods of forming the same 有权
公开(公告)号：US10244637B2
公开(公告)日：2019-03-26
申请号：US13206279
申请日：2011-08-09
申请人： David Jones , Florian Pschenitzka , Xina Quan , Michael A. Spaid , Jeffrey Wolk
发明人： David Jones , Florian Pschenitzka , Xina Quan , Michael A. Spaid , Jeffrey Wolk
IPC分类号： G02F1/1343 , H05K3/24 , B82Y10/00 , B82Y30/00 , H01L31/18 , H01L29/41 , H01L51/00 , H01L51/52 , H05K1/09 , H01L29/06
摘要： Composite transparent conductors are described, which comprise a primary conductive medium based on metal nanowires and a secondary conductive medium based on a continuous conductive film.

46. 发明授权

US10211329B2 Charge trapping prevention III-Nitride transistor 有权
公开(公告)号：US10211329B2
公开(公告)日：2019-02-19
申请号：US15184032
申请日：2016-06-16
申请人： Infineon Technologies Americas Corp.
发明人： Hyeongnam Kim , Mohamed Imam , Alain Charles , Jianwei Wan , Mihir Tungare , Chan Kyung Choi
IPC分类号： H01L29/778 , H01L29/20 , H01L29/41 , H01L29/205 , H01L29/417 , H01L29/423 , H01L29/43 , H01L29/06
摘要： There are disclosed herein various implementations of a charge trapping prevention III-Nitride transistor. Such a transistor may be a III-Nitride high electron mobility transistor (HEMT) including a III-Nitride intermediate body situated over a substrate, a channel layer situated over the III-Nitride intermediate body, and a barrier layer situated over the channel layer. The channel layer and the barrier layer are configured to produce a two-dimensional electron gas (2DEG). In addition, the III-Nitride transistor includes a dielectric layer situated over the barrier layer, a gate coupled to the barrier layer, and a drain electrode and a source electrode each extending through the dielectric layer. The drain electrode makes ohmic contact with one or both of the barrier layer and a charge trapping prevention layer situated between the dielectric layer and the barrier layer.

47. 发明授权

US10199505B2 Transistors incorporating metal quantum dots into doped source and drain regions 有权
公开(公告)号：US10199505B2
公开(公告)日：2019-02-05
申请号：US15620444
申请日：2017-06-12
申请人： STMicroelectronics, Inc.
发明人： John H. Zhang
IPC分类号： H01L29/786 , H01L29/775 , H01L29/66 , H01L29/40 , H01L29/417 , H01L29/778 , H01L29/41 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/12 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/165
摘要： Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

48. 发明授权

US10192826B2 Conductive layout structure including high resistive layer 有权
公开(公告)号：US10192826B2
公开(公告)日：2019-01-29
申请号：US15853978
申请日：2017-12-26
申请人： UNITED MICROELECTRONICS CORP.
发明人： Kun-Ju Li , Kuo-Chin Hung , Min-Chuan Tsai , Wei-Chuan Tsai , Yi-Han Liao , Chun-Tsen Lu , Fu-Shou Tsai , Li-Chieh Hsu
IPC分类号： H01L23/52 , H01L29/41 , H01L23/528 , H01L23/532 , H01L23/485 , H01L21/768 , H01L23/522 , H01L29/417 , H01L29/66 , H01L29/78
摘要： A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.

49. 发明授权

US10164030B2 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US10164030B2
公开(公告)日：2018-12-25
申请号：US15604687
申请日：2017-05-25
申请人： Samsung Electronics Co., Ltd.
发明人： Jin-bum Kim , Chul-sung Kim , Deok-han Bae , Bon-young Koo
IPC分类号： H01L29/41 , H01L21/82 , H01L27/092 , H01L29/66 , H01L29/417 , H01L29/78 , H01L29/165 , H01L21/8238
摘要： A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

50. 发明授权

US10164019B2 Semiconductor device and a method for forming a semiconductor 有权
公开(公告)号：US10164019B2
公开(公告)日：2018-12-25
申请号：US15210106
申请日：2016-07-14
申请人： Infineon Technologies AG
发明人： Roland Rupp , Guenther Ruhl , Hans-Joachim Schulze
IPC分类号： H01L29/15 , H01L29/16 , H01L29/36 , H01L29/08 , H01L29/417 , H01L21/02 , H01L21/265 , H01L21/324 , H01L29/41
摘要： A method for forming a semiconductor device includes forming at least one graphene layer on a surface of a semiconductor substrate. The method further includes forming a silicon carbide layer on the at least one graphene layer.

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