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51. 发明授权

US07799512B2 Method for forming ring pattern 有权
标题翻译：形成环形图案的方法
公开(公告)号：US07799512B2
公开(公告)日：2010-09-21
申请号：US11742272
申请日：2007-04-30
申请人： Kuo-Yao Cho , Jen-Jui Huang
发明人： Kuo-Yao Cho , Jen-Jui Huang
IPC分类号： G03F7/26
CPC分类号： H01L21/31144 , H01L21/0337
摘要： A method for forming a ring pattern is disclosed. The ring pattern has a first wall and a second wall. The method includes the following steps: (a) providing a substrate; (b) forming a dielectric layer on the substrate; (c) forming a first patterned photoresist layer on the dielectric layer, the first patterned photoresist layer defining the first wall; (d) etching the dielectric layer to a predetermined depth by using the first patterned photoresist as a mask, and then removing the first patterned photoresist layer; (e) forming a second patterned photoresist layer on the dielectric layer, the second patterned photoresist layer defining the second wall; (f) etching the dielectric layer by using the second patterned photoresist layer as a mask so as to form the ring pattern having the first wall and the second wall.
摘要翻译：公开了一种形成环形图案的方法。环形图案具有第一壁和第二壁。该方法包括以下步骤：（a）提供衬底; （b）在基板上形成电介质层; （c）在所述电介质层上形成第一图案化光致抗蚀剂层，所述第一图案化光刻胶层限定所述第一壁; （d）通过使用第一图案化的光致抗蚀剂作为掩模将电介质层蚀刻到预定的深度，然后去除第一图案化的光致抗蚀剂层; （e）在所述电介质层上形成第二图案化光致抗蚀剂层，所述第二图案化光致抗蚀剂层限定所述第二壁; （f）通过使用第二图案化光致抗蚀剂层作为掩模蚀刻介电层，以便形成具有第一壁和第二壁的环形图案。

52. 发明授权

US07746165B1 Voltage selecting circuit, voltage providing circuit utilizing the voltage selecting circuit, and signal delaying system utilizing the voltage providing circuit 有权
标题翻译：电压选择电路，利用电压选择电路的电压提供电路和利用电压提供电路的信号延迟系统
公开(公告)号：US07746165B1
公开(公告)日：2010-06-29
申请号：US12357376
申请日：2009-01-21
申请人： Chih-Jen Chen
发明人： Chih-Jen Chen
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/56 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/40615 , G11C11/4074 , G11C11/4076 , G11C2211/4065 , G11C2211/4067
摘要： A voltage providing circuit includes: a first voltage providing circuit, for generating a first voltage; a switch device, for receiving a first voltage; a second voltage providing circuit, for providing a second voltage; a control circuit, for controlling the switch device and the second voltage providing circuit, wherein in a first mode, the control circuit turns off the switch device for allowing a target device to receive the second voltage, and in a second mode, the control circuit turns on the switch device and stops the second voltage providing circuit from providing the second voltage such that the target device can receive the first voltage; and an adjusting circuit, for providing a reference voltage to the first voltage providing circuit according to the first voltage and the second voltage for changing the first voltage, thereby making the first voltage substantially equal to the second voltage.
摘要翻译：电压提供电路包括：第一电压提供电路，用于产生第一电压; 用于接收第一电压的开关装置; 第二电压提供电路，用于提供第二电压; 用于控制开关装置和第二电压提供电路的控制电路，其中在第一模式中，所述控制电路关断所述开关装置以允许目标装置接收所述第二电压，并且在第二模式中，所述控制电路打开开关装置，停止第二电压提供电路提供第二电压，使得目标装置可以接收第一电压; 以及调整电路，用于根据用于改变第一电压的第一电压和第二电压向第一电压提供电路提供参考电压，从而使第一电压基本上等于第二电压。

53. 发明授权

US07663391B2 Test system and method for reducing test signal loss for integrated circuits 有权
标题翻译：用于降低集成电路测试信号损耗的测试系统和方法
公开(公告)号：US07663391B2
公开(公告)日：2010-02-16
申请号：US12039742
申请日：2008-02-29
申请人： Shun-Ker Wu
发明人： Shun-Ker Wu
IPC分类号： G01R31/26
CPC分类号： G01R31/2886 , G01R31/2822
摘要： An integrated circuit test system includes a probe card, a driver, a receiver, and a first switch. The driver is coupled to the probe card via a first signal line. The receiver is coupled to the probe card via a second signal line. The first switch is coupled between the probe card and the first signal line. After the driver outputs a test signal to a device under test via the first signal line, the first switch is turned off, and then the receiver reads the test signal via the second signal line. Thus, the test signal loss can be reduced.
摘要翻译：集成电路测试系统包括探针卡，驱动器，接收器和第一开关。驱动器经由第一信号线耦合到探针卡。接收器经由第二信号线耦合到探针卡。第一开关耦合在探针卡和第一信号线之间。在驱动器通过第一条信号线将测试信号输出到被测器件后，第一个开关被关闭，然后接收器通过第二个信号线读取测试信号。因此，可以减少测试信号损失。

54. 发明授权

US07651824B1 Method for compensating critical dimension variations in photomasks 有权
标题翻译：补偿光掩模中临界尺寸变化的方法
公开(公告)号：US07651824B1
公开(公告)日：2010-01-26
申请号：US12329628
申请日：2008-12-07
申请人： Hsuan-Ko Chen , Mei-Li Wang , Chih-Cheng Chin , Pei-Cheng Fan
发明人： Hsuan-Ko Chen , Mei-Li Wang , Chih-Cheng Chin , Pei-Cheng Fan
IPC分类号： G03F9/00
CPC分类号： G03F7/70625 , G03F1/50 , G03F1/70 , G03F7/70283 , G03F7/70383 , G03F7/70433
摘要： A method for compensating critical dimension (CD) variations of patterns of a substrate, by the correcting the CD of the corresponding photomask is disclosed. First, a light and a main photomask are provided. Second, an auxiliary photomask including an auxiliary transparent substrate and a shading element within the auxiliary transparent substrate is provided. Next the light passes through the auxiliary photomask and main photomask in order for compensating CD variations of patterns corresponding to main photomask.
摘要翻译：公开了通过校正相应光掩模的CD来补偿衬底图案的临界尺寸（CD）变化的方法。首先，提供光和主光掩模。其次，提供在副透明基板内配置有辅助透明基板和遮光元件的辅助光掩模。接下来，光通过辅助光掩模和主光掩模，以补偿对应于主光掩模的图案的CD变化。

55. 发明授权

US07642191B2 Method of forming semiconductor structure 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US07642191B2
公开(公告)日：2010-01-05
申请号：US12019260
申请日：2008-01-24
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/311
CPC分类号： H01L21/823481 , H01L21/823437 , H01L27/115 , H01L27/11521
摘要： A method of forming a semiconductor structure is provided. The method includes providing a substrate and forming a mask layer on the substrate, Next, dielectric isolations are formed in the mask layer and the substrate, wherein the dielectric isolations extend above the substrate. Then, the mask layer is removed to expose a portion of the substrate, and a dielectric layer is formed on the exposed portion of the substrate. Subsequently, a first conductive layer is formed on the dielectric layer, and a portion of the dielectric isolation is removed, wherein a top surface of the remaining dielectric isolation is lower than a top surface of the first conductive layer. Moreover, a conformal layer is formed over the substrate, and a second conductive layer is formed on the conformal layer.
摘要翻译：提供一种形成半导体结构的方法。该方法包括提供衬底并在衬底上形成掩模层。接下来，在掩模层和衬底中形成介电隔离，其中介电隔离物延伸到衬底上方。然后，去除掩模层以露出衬底的一部分，并且在衬底的暴露部分上形成电介质层。随后，在电介质层上形成第一导电层，去除介电隔离的一部分，其中绝缘隔离的顶表面低于第一导电层的顶表面。此外，在衬底上形成保形层，并且在保形层上形成第二导电层。

56. 发明申请

US20090296779A1 TEMPERATURE DETECTOR AND THE METHOD USING THE SAME 有权
标题翻译：温度检测器及其使用方法
公开(公告)号：US20090296779A1
公开(公告)日：2009-12-03
申请号：US12186672
申请日：2008-08-06
申请人： Wen Ming Lee
发明人： Wen Ming Lee
IPC分类号： G01K7/01
CPC分类号： G01K7/01 , G01K2219/00
摘要： A temperature detector includes a plurality of comparators, an electronic component and a controller. Each of the comparators is responsible for detecting different temperature ranges. The electronic component has a temperature-dependent threshold voltage and an output connected to inputs of the plurality of comparators. The controller is configured to enable only one of the comparators at one time and to generate a value to the other inputs of the plurality of comparators.
摘要翻译：温度检测器包括多个比较器，电子部件和控制器。每个比较器负责检测不同的温度范围。电子部件具有与温度相关的阈值电压和与多个比较器的输入相连的输出。控制器被配置为一次仅使能一个比较器并且为多个比较器的其他输入产生一个值。

57. 发明授权

US07622381B2 Semiconductor structure and the forming method thereof 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US07622381B2
公开(公告)日：2009-11-24
申请号：US11829371
申请日：2007-07-27
申请人： Jar-Ming Ho , Shian-Jyh Lin , Ming-Yuan Huang
发明人： Jar-Ming Ho , Shian-Jyh Lin , Ming-Yuan Huang
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76897 , H01L21/76834 , H01L27/10888 , H01L27/10894
摘要： The present invention provides a semiconductor structure and the forming method thereof. The structure includes a substrate having a plurality of stacks; a conformal layer on the substrate and a portion of sidewalls of the plurality of the stacks; and a plurality of plugs between the plurality of stacks. In addition, the present invention also provides a method of forming the semiconductor structure, comprising steps of providing a substrate; forming a plurality of stacks on the substrate; forming a conformal layer on the stacks and on the substrate; removing a portion of the conformal layer to expose a sidewall and a top surface of the plurality of stacks; and forming a plurality of plugs between the stacks.
摘要翻译：本发明提供一种半导体结构及其形成方法。该结构包括具有多个堆叠的基板; 所述衬底上的共形层和所述多个所述堆叠中的侧壁的一部分; 以及多个堆叠之间的多个插头。此外，本发明还提供一种形成半导体结构的方法，包括提供衬底的步骤; 在所述基板上形成多个堆叠; 在堆叠和基板上形成共形层; 去除所述共形层的一部分以暴露所述多个叠层的侧壁和顶表面; 以及在所述堆叠之间形成多个塞子。

58. 发明申请

US20090166702A1 TRENCH-TYPE SEMICONDUCTOR DEVICE STRUCTURE 有权
标题翻译： TRENCH型半导体器件结构
公开(公告)号：US20090166702A1
公开(公告)日：2009-07-02
申请号：US12177756
申请日：2008-07-22
申请人： Shian-Jyh LIN , Ming-Cheng Chang , Neng Tai Shih , Hung-Chang Liao
发明人： Shian-Jyh LIN , Ming-Cheng Chang , Neng Tai Shih , Hung-Chang Liao
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867 , H01L28/55
摘要： A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings.
摘要翻译：公开了一种沟槽型半导体器件结构。该结构包括半导体衬底，栅介质层和衬底沟道结构。半导体衬底包括具有上部和下部的沟槽。上部包括形成在其中的导电层。下部包括形成在其中的沟槽电容器。栅极电介质层位于半导体衬底和导电层之间。具有与沟槽相邻的开口的衬底沟道结构经由开口电连接到半导体衬底。

59. 发明授权

US07553737B2 Method for fabricating recessed-gate MOS transistor device 有权
标题翻译：凹槽栅极MOS晶体管器件的制造方法
公开(公告)号：US07553737B2
公开(公告)日：2009-06-30
申请号：US11673597
申请日：2007-02-12
申请人： Ming-Yuan Huang , Jar-Ming Ho
发明人： Ming-Yuan Huang , Jar-Ming Ho
IPC分类号： H01L21/20
CPC分类号： H01L21/823437 , H01L21/823487 , H01L27/10861 , H01L27/10876
摘要： A method of fabricating gate trench utilizing pad pullback technology is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad layer is provided. Trench capacitors are formed in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. The pad layer is recessed from its top and covered with a polysilicon layer. Isolation trenches are formed in the substrate and then filled with photoresist. The TTO is then stripped. The pad layer that is not covered by the photoresist is pulled back to define the gate trench.
摘要翻译：公开了一种利用焊盘回退技术制造栅极沟槽的方法。提供了具有衬垫氧化物层和焊盘层的半导体衬底。沟槽电容器形成在半导体衬底的存储器阵列区域中。每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。衬垫层从其顶部凹陷并覆盖有多晶硅层。在衬底中形成绝缘沟槽，然后用光刻胶填充。然后剥离TTO。未被光致抗蚀剂覆盖的焊盘层被拉回以限定栅极沟槽。

60. 发明申请

US20090124085A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAS A LENGTHENED CHANNEL LENGTH 审中-公开
标题翻译：形成半导体器件的方法具有增加的通道长度
公开(公告)号：US20090124085A1
公开(公告)日：2009-05-14
申请号：US12019178
申请日：2008-01-24
申请人： Hung-Ming TSAI , Ying Cheng CHUANG
发明人： Hung-Ming TSAI , Ying Cheng CHUANG
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/76232 , H01L29/1037
摘要： The present invention discloses a method for forming a semiconductor device. The method includes providing a substrate; forming at least one first opening in the substrate to a predetermined depth and exposing a sidewall of the substrate in the first opening; forming a spacer on the sidewall and exposing a portion of the substrate in the bottom of the first opening; etching the exposed substrate in the bottom of the first opening by using the spacer as a mask to form a second opening; forming an isolation layer in the second opening and a portion of the first opening; forming a gate dielectric layer on the surface of the substrate; and forming a conductive layer covering the substrate.
摘要翻译：本发明公开了一种形成半导体器件的方法。该方法包括提供基板; 在所述基板中形成至少一个第一开口至预定深度，并在所述第一开口中暴露所述基板的侧壁; 在所述侧壁上形成间隔物并暴露所述第一开口底部中的所述基底的一部分; 通过使用间隔件作为掩模来蚀刻第一开口的底部中的暴露的基板以形成第二开口; 在所述第二开口中形成隔离层和所述第一开口的一部分; 在所述基板的表面上形成栅极电介质层; 以及形成覆盖所述基板的导电层。

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