专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US07183627B2 Independent control of polycrystalline silicon-germanium in an HBT and related structure 有权
标题翻译：独立控制HBT及相关结构中的多晶硅锗
公开(公告)号：US07183627B2
公开(公告)日：2007-02-27
申请号：US10054438
申请日：2002-01-22
申请人： Gregory D. U'ren
发明人： Gregory D. U'ren
IPC分类号： H01L27/082
CPC分类号： H01L29/66242 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262
摘要： In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.
摘要翻译：在一个实施方案中，提供用于生长多晶硅 - 锗区和单晶硅 - 锗区的前体气体。前体气体可以是例如GeH 4 N 4。多晶硅锗区可以是例如异质结双极晶体管中的基极接触，而单晶硅 - 锗区可以是例如异质结双极晶体管中的基极。多晶硅锗区域可以在一定温度和一定压力的前体气体的质量控制模式下生长，同时可以在相同温度的动态控制模式下同时生长单晶硅 - 锗区域，相同的前体气体压力。所公开的实施例导致独立于单晶硅 - 锗的生长来控制多晶硅 - 锗的生长。

52. 发明授权

US07154161B1 Composite ground shield for passive components in a semiconductor die 有权
标题翻译：半导体芯片中无源器件的复合接地屏蔽
公开(公告)号：US07154161B1
公开(公告)日：2006-12-26
申请号：US10826507
申请日：2004-04-16
申请人： Volker A. Blaschke , Marco Racanelli
发明人： Volker A. Blaschke , Marco Racanelli
IPC分类号： H01L29/00
CPC分类号： H01L23/5227 , H01L21/76838 , H01L28/10 , H01L2924/0002 , Y10S257/904 , H01L2924/00
摘要： According to one exemplary embodiment, a structure situated in a semiconductor die comprises an active shield situated in a substrate, where the active shield comprises a salicide layer situated on an active region, and where the active shield has a first conductivity type. The active shield can be situated in a well in the substrate, where the well is connected to a voltage source greater than or equal to a ground voltage, and where the well has a second conductivity type. According to this exemplary embodiment, the structure further comprises a passive component situated in an interconnect metal layer in the semiconductor die, where the passive component is situated above the active shield, and where the active shield defines an AC ground for the passive component. The structure further comprises at least one contact, where the at least one contact connects the active shield to a semiconductor die AC ground.
摘要翻译：根据一个示例性实施例，位于半导体管芯中的结构包括位于衬底中的有源屏蔽，其中主动屏蔽包括位于有源区上的自对准层，并且其中主动屏蔽具有第一导电类型。主动屏蔽可以位于衬底中的阱中，其中阱连接到大于或等于接地电压的电压源，并且阱具有第二导电类型。根据该示例性实施例，该结构还包括位于半导体管芯中的互连金属层中的无源部件，其中无源部件位于主动屏蔽之上，并且其中主动屏蔽件限定用于无源部件的AC接地。该结构还包括至少一个触点，其中至少一个触点将有源屏蔽连接到半导体管芯AC地。

53. 发明授权

US07109125B1 Selective fabrication of high capacitance density areas in a low dielectric constant material 有权
标题翻译：在低介电常数材料中选择性地制造高电容密度区域
公开(公告)号：US07109125B1
公开(公告)日：2006-09-19
申请号：US10995762
申请日：2004-11-22
申请人： Q. Z. Liu , David Feiler , Bin Zhao , Phil N. Sherman , Maureen Brongo
发明人： Q. Z. Liu , David Feiler , Bin Zhao , Phil N. Sherman , Maureen Brongo
IPC分类号： H01L21/302 , H01L21/461 , H01L21/20 , H01L21/8242
CPC分类号： H01L28/86 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Method for selective fabrication of high capacitance density areas in a low dielectric constant material and related structure are disclosed. In one embodiment, a first area of a dielectric layer is covered, for example with photoresist, while a second area of the dielectric layer is exposed to a dielectric conversion source such as E-beams, I-beams, oxygen plasma, or an appropriate chemical. The exposure causes the dielectric constant of the dielectric layer in the second area to increase. A number of capacitor trenches are etched in the second area of the dielectric. The capacitor trenches are then filled with an appropriate metal, such as copper, and a chemical mechanical polish is performed. The second area in which the capacitor trenches have been etched and filled has a higher capacitance density relative to the first area. In another embodiment, the exposure to the dielectric conversion source is not performed until after the chemical mechanical polish has been performed. In yet another embodiment, a blanket layer of metal, such as aluminum, is first deposited. The blanket layer of metal is then etched to form metal lines. Then a gap fill dielectric is utilized to fill the gaps between the remaining metal lines. A first area of the gap fill dielectric is then covered and a second area of the gap fill dielectric is exposed to a dielectric conversion source. After exposure to the dielectric conversion source, the dielectric constant of the gap fill dielectric in the second area increases. The metal lines in the second area can then be used as capacitor electrodes of a high density capacitor.
摘要翻译：公开了用于选择性地制造低介电常数材料和相关结构中的高电容密度区域的方法。在一个实施例中，电介质层的第一区域例如被光致抗蚀剂覆盖，而介电层的第二区域暴露于电介质转换源（例如电子束，I型波束，氧等离子体）或适当的化学品。曝光导致第二区域中介电层的介电常数增加。在电介质的第二区域中蚀刻多个电容器沟槽。然后用适当的金属（例如铜）填充电容器沟槽，并进行化学机械抛光。其中电容器沟槽被蚀刻和填充的第二区域相对于第一区域具有较高的电容密度。在另一个实施例中，直到进行化学机械抛光之后，不进行介电转换源的曝光。在又一实施例中，首先沉积诸如铝的金属覆盖层。然后蚀刻金属覆盖层以形成金属线。然后使用间隙填充电介质来填充剩余金属线之间的间隙。然后覆盖间隙填充电介质的第一区域，并且间隙填充电介质的第二区域暴露于电介质转换源。在暴露于电介质转换源之后，第二区域中间隙填充电介质的介电常数增加。然后可以将第二区域中的金属线用作高密度电容器的电容器电极。

54. 发明授权

US07064415B1 Self-aligned bipolar transistor having increased manufacturability 有权
标题翻译：具有增加的可制造性的自对准双极晶体管
公开(公告)号：US07064415B1
公开(公告)日：2006-06-20
申请号：US10995769
申请日：2004-11-22
申请人： Amol Kalburge , Kevin Q. Yin , Kenneth Ring
发明人： Amol Kalburge , Kevin Q. Yin , Kenneth Ring
IPC分类号： H01L27/082
CPC分类号： H01L29/66242
摘要： According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.
摘要翻译：根据一个示例性实施例，双极晶体管包括具有顶表面的基座。双极晶体管还包括位于基底的顶表面上的基底氧化物层。双极晶体管还包括位于基底氧化物层上的牺牲柱。双极晶体管还包括位于基底的牺牲柱和顶表面之上的共形层，其中共形层的密度大于基底氧化物层的密度。保形层可以是例如HDPCVD氧化物。根据该示例性实施例，双极晶体管还包括位于保形层之上的牺牲平坦化层。牺牲平坦化层在第一和第二连接间隔物之间的第一区域中具有第一厚度，在第一和第二连接间隔物的第二区域中具有第二厚度，其中第二厚度通常大于第一厚度。

55. 发明授权

US07064073B1 Technique for reducing contaminants in fabrication of semiconductor wafers 有权
标题翻译：减少半导体晶片制造中污染物的技术
公开(公告)号：US07064073B1
公开(公告)日：2006-06-20
申请号：US10434961
申请日：2003-05-09
申请人： Gregory D. U'ren
发明人： Gregory D. U'ren
IPC分类号： H01L21/302
CPC分类号： C23C16/4405
摘要： According to one embodiment, a method for reducing contaminants in a reactor chamber is disclosed where the method comprises a step of etching the reactor chamber, which can comprise, for example, a dry etch process performed with hydrogen and HCL. Next, the reactor chamber is baked, which can comprise, for example, baking with hydrogen. Thereafter, an undoped semiconductor layer, such as an undoped silicon layer, is deposited in the reactor chamber to form a sacrificial semiconductor layer, for example, a sacrificial silicon layer. Then, the sacrificial semiconductor layer, for example, the sacrificial silicon layer, is removed from the reactor chamber. The removal step can comprise, for example, a dry etch process performed with HCL. In another embodiment, a wafer is fabricated in a reactor chamber that is substantially free of contaminants due to the implementation of the above method.
摘要翻译：根据一个实施例，公开了一种用于减少反应器室中的污染物的方法，其中该方法包括蚀刻反应器室的步骤，其可以包括例如用氢和HCL进行的干蚀刻工艺。接下来，将反应器室烘烤，其可以包括例如用氢气烘烤。此后，将未掺杂的半导体层，例如未掺杂的硅层沉积在反应器室中以形成牺牲半导体层，例如牺牲硅层。然后，将牺牲半导体层，例如牺牲硅层从反应器室中移除。去除步骤可以包括例如用HCL进行的干蚀刻工艺。在另一个实施方案中，由于实施上述方法，晶片被制造在基本上不含污染物的反应器室中。

56. 发明授权

US07056822B1 Method of fabricating an interconnect structure employing air gaps between metal lines and between metal layers 有权
标题翻译：制造在金属线之间和金属层之间采用气隙的互连结构的方法
公开(公告)号：US07056822B1
公开(公告)日：2006-06-06
申请号：US09686323
申请日：2000-10-09
申请人： Bin Zhao
发明人： Bin Zhao
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/4821 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and fabrication method are provided to form air gaps between interconnect lines and between interconnect layers. A conductive material is deposited and patterned to form a first level of interconnect lines. A first dielectric layer is deposited over the first level of interconnect lines. One or more air gaps are formed in the first dielectric layer to reduce inter-layer capacitance, intra-layer capacitance or both inter-layer and intra-layer capacitance. At least one support pillar remains in the first dielectric layer to promote mechanical strength and thermal conductivity. A sealing layer is deposited over the first insulative layer to seal the air gaps. Via holes are patterned and etched through the sealing layer and the first dielectric layer. A conductive material is deposited to fill the via holes and form conductive plugs therein. Thereafter, a conductive material is deposited and patterned to form a second level of interconnect lines.
摘要翻译：提供互连结构和制造方法以在互连线之间和互连层之间形成气隙。导电材料被沉积并图案化以形成第一级互连线。第一介电层沉积在第一级互连线上。在第一介电层中形成一个或多个空气间隙，以减少层间电容，层间电容或层间电容和层间电容。至少一个支撑柱保留在第一介电层中以促进机械强度和导热性。密封层沉积在第一绝缘层上以密封气隙。图案化通孔并通过密封层和第一介电层蚀刻。沉积导电材料以填充通孔并在其中形成导电塞。此后，沉积并图案化导电材料以形成第二级互连线。

57. 发明授权

US07033898B1 Method for fabricating a self-aligned bipolar transistor having recessed spacers 有权
标题翻译：制造具有凹进间隔物的自对准双极晶体管的方法
公开(公告)号：US07033898B1
公开(公告)日：2006-04-25
申请号：US10865153
申请日：2004-06-09
申请人： Amol Kalburge , Kevin Q. Yin
发明人： Amol Kalburge , Kevin Q. Yin
IPC分类号： H01L21/8222 , H01L21/331
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/66242
摘要： According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated between the first and second link spacers, where the first and second link spacers have a height that is substantially less than a height of the sacrificial post. The bipolar transistor also comprises a conformal layer situated over the sacrificial post and the first and second link spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the first and second link spacers, the sacrificial post, and the base. The sacrificial planarizing layer may comprise, for example, an organic material such as an organic BARC (“bottom anti-reflective coating”).
摘要翻译：根据一个示例性实施例，双极晶体管包括具有顶表面的基座。双极晶体管还包括第一连接间隔物和位于基底的顶表面上的第二连接间隔物。所述双极晶体管还包括位于所述第一和第二连接间隔件之间的牺牲柱，其中所述第一和第二连接间隔件的高度实质上小于所述牺牲柱的高度。双极晶体管还包括位于牺牲柱和第一和第二连接间隔物之上的共形层。根据该示例性实施例，双极晶体管还包括位于保形层之上的牺牲平坦化层，第一和第二连接间隔物，牺牲柱和基底。牺牲平坦化层可以包括例如有机材料，例如有机BARC（“底部抗反射涂层”）。

58. 发明授权

US07015115B1 Method for forming deep trench isolation and related structure 有权
标题翻译：形成深沟槽隔离及相关结构的方法
公开(公告)号：US07015115B1
公开(公告)日：2006-03-21
申请号：US10371307
申请日：2003-02-20
申请人： Kevin Q. Yin , Amol Kalburge
发明人： Kevin Q. Yin , Amol Kalburge
IPC分类号： H01L21/76
CPC分类号： H01L21/76202 , H01L21/763
摘要： According to one embodiment, a structure comprises a substrate and a field oxide region, where the field oxide region has a top surface, and where the top surface of the field oxide region comprises substantially no cavities caused by lateral etching. The structure further comprises a trench situated in the substrate, where the trench has a first sidewall and a second sidewall in the substrate, and where the trench is situated directly underneath the field oxide region. According to this embodiment, the trench is used as a deep trench isolation region in the substrate and is typically filled with polysilicon. A thermally grown oxide liner is situated on the first and the second sidewalls of the trench, where the oxide liner is formed after removal of a hard mask. The hard mask may be densified TEOS oxide or HDP oxide and may be removed in an anisotropic dry etch process.
摘要翻译：根据一个实施例，结构包括衬底和场氧化物区域，其中场氧化物区域具有顶表面，并且其中场氧化物区域的顶表面基本上不包括由侧向蚀刻引起的空腔。该结构还包括位于衬底中的沟槽，其中沟槽在衬底中具有第一侧壁和第二侧壁，并且其中沟槽位于场氧化物区域的正下方。根据该实施例，沟槽用作衬底中的深沟槽隔离区域，并且通常填充有多晶硅。热生长的氧化物衬垫位于沟槽的第一和第二侧壁上，其中在去除硬掩模之后形成氧化物衬垫。硬掩模可以是致密的TEOS氧化物或HDP氧化物，并且可以在各向异性干蚀刻工艺中除去。

59. 发明授权

US06984577B1 Damascene interconnect structure and fabrication method having air gaps between metal lines and metal layers 有权
标题翻译：具有金属线和金属层之间气隙的镶嵌互连结构和制造方法
公开(公告)号：US06984577B1
公开(公告)日：2006-01-10
申请号：US09665422
申请日：2000-09-20
申请人： Bin Zhao , Maureen R. Brongo
发明人： Bin Zhao , Maureen R. Brongo
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76802 , H01L21/76807 , H01L21/7681 , H01L21/76832 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A damascene interconnect that reduces interconnect intra-layer capacitance and/or inter-layer capacitance is provided. The damascene interconnect structure has air gaps between metal lines and/or metal layers. The interconnect structure is fabricated to a via level through a processing step prior to forming contact vias, then one or more air gaps are formed into the damascene structure so that the air gaps are positioned between selected metal lines. A sealing layer is then deposited over the damascene structure to seal the air gaps.
摘要翻译：提供了减少互连层内电容和/或层间电容的镶嵌互连。镶嵌互连结构在金属线和/或金属层之间具有气隙。在形成接触通孔之前，通过处理步骤将互连结构制成通孔级，然后将一个或多个气隙形成到镶嵌结构中，使得气隙位于选定的金属线之间。然后将密封层沉积在镶嵌结构上以密封气隙。

60. 发明授权

US06867440B1 Self-aligned bipolar transistor without spacers and method for fabricating same 有权
标题翻译：无衬垫的自对准双极晶体管及其制造方法
公开(公告)号：US06867440B1
公开(公告)日：2005-03-15
申请号：US10442501
申请日：2003-05-21
申请人： Amol M Kalburge , Kevin Q. Yin
发明人： Amol M Kalburge , Kevin Q. Yin
IPC分类号： H01L21/331 , H01L29/08 , H01L31/0328
CPC分类号： H01L29/66242 , H01L29/0804 , H01L29/66287
摘要： According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated on a first and a second side of the sacrificial post, where the conformal layer is not separated from the first and second sides of the sacrificial post by spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second sides of the sacrificial post and a second thickness in a second region outside of the first and second sides of the sacrificial post, where the second thickness is greater than the first thickness.
摘要翻译：根据一个示例性实施例，双极晶体管包括具有顶表面的基座。双极晶体管还包括位于基底的顶表面上的牺牲柱。双极晶体管还包括位于牺牲柱的第一和第二侧上的共形层，其中共形层不通过间隔物与牺牲柱的第一和第二侧分离。根据该示例性实施例，双极晶体管还包括位于保形层，牺牲柱和基底之上的牺牲平坦化层。牺牲平坦化层在牺牲柱的第一和第二侧之间的第一区域中具有第一厚度，在牺牲柱的第一和第二侧外侧的第二区域中具有第二厚度，其中第二厚度大于第一厚度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式