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51. 发明申请

US20150210533A1 SENSOR STRUCTURES, SYSTEMS AND METHODS WITH IMPROVED INTEGRATION AND OPTIMIZED FOOTPRINT 有权
标题翻译：传感器结构，系统和方法与改进的集成和优化的FOOTPRINT
公开(公告)号：US20150210533A1
公开(公告)日：2015-07-30
申请号：US14163205
申请日：2014-01-24
申请人： Infineon Technologies Dresden GmbH
发明人： Thoralf Kautzsch , Heiko Fröhlich , Mirko Vogt , Maik Stegemann , Andre Röth , Bernhard Winkler , Boris Binder
IPC分类号： B81B3/00 , G01L9/00
CPC分类号： G01L9/0072 , B81B2201/0264 , B81B2203/0127 , B81C1/00158 , G01L9/0041 , G01L9/0073
摘要： Embodiments relate to sensors and more particularly to structures for and methods of forming sensors that are easier to manufacture as integrated components and provide improved deflection of a sensor membrane, lamella or other movable element. In embodiments, a sensor comprises a support structure for a lamella, membrane or other movable element. The support structure comprises a plurality of support elements that hold or carry the movable element. The support elements can comprise individual points or feet-like elements, rather than a conventional interconnected frame, that enable improved motion of the movable element, easier removal of a sacrificial layer between the movable element and substrate during manufacture and a more favorable deflection ratio, among other benefits.
摘要翻译：实施例涉及传感器，更具体地涉及形成传感器的结构和方法，所述传感器更容易制造为集成部件并提供传感器膜，薄片或其它可移动元件的改进偏转。在实施例中，传感器包括用于薄片，膜或其它可移动元件的支撑结构。支撑结构包括保持或承载可移动元件的多个支撑元件。支撑元件可以包括单个点或脚状元件，而不是传统的互连框架，其能够改善可移动元件的运动，在制造期间更容易地去除可移动元件和基板之间的牺牲层，并且具有更有利的偏移比，其他好处。

52. 发明申请

US20150162253A1 CARRIER AND A METHOD FOR PROCESSING A CARRIER 有权
标题翻译：载体和加工载体的方法
公开(公告)号：US20150162253A1
公开(公告)日：2015-06-11
申请号：US14098570
申请日：2013-12-06
申请人： Infineon Technologies Dresden GmbH
发明人： Steffen Bieselt
IPC分类号： H01L23/053 , B23Q3/18 , H01L21/48 , H01L23/08 , H01L23/498
CPC分类号： H01L21/764 , B23Q3/18 , H01L21/4803 , H01L21/481 , H01L23/053 , H01L23/08 , H01L23/13 , H01L23/147 , H01L23/34 , H01L23/498 , H01L2924/0002 , Y10T29/49155 , H01L2924/00
摘要： According to various embodiments, a carrier may be provided, the carrier including: a hollow chamber spaced apart from a surface of the carrier; a trench structure extending from the surface of the carrier to the hollow chamber and laterally surrounding a first region of the carrier, the trench structure including one or more trenches extending from the surface of the carrier to the hollow chamber, and one or more support structures intersecting the one or more trenches and connecting the first region of the carrier with a second region of the carrier outside the trench structure, wherein the one or more support structures including an electrically insulating material.
摘要翻译：根据各种实施例，可以提供载体，载体包括：与载体的表面间隔开的中空室; 沟槽结构，其从所述载体的表面延伸到所述中空室并横向围绕所述载体的第一区域，所述沟槽结构包括从所述载体的所述表面延伸到所述中空室的一个或多个沟槽，以及一个或多个支撑结构与所述一个或多个沟槽交叉并且将所述载体的所述第一区域与所述载体的第二区域连接到所述沟槽结构外部，其中所述一个或多个支撑结构包括电绝缘材料。

53. 发明申请

US20150115226A1 OPTOELECTRONIC COMPONENT, A METHOD FOR MANUFACTURING AN OPTOELECTRONIC COMPONENT, AND A METHOD FOR PROCESSING A CARRIER 有权
标题翻译：光电子元件，制造光电元件的方法和用于处理载体的方法
公开(公告)号：US20150115226A1
公开(公告)日：2015-04-30
申请号：US14064302
申请日：2013-10-28
申请人： Infineon Technologies Dresden GmbH
发明人： Alessia Scire , Dieter Kaiser , Tarja Hauck , Frank Zschorlich
IPC分类号： H01L31/16 , H01L27/28
CPC分类号： H01L51/56 , H01L27/288 , H01L27/3276 , H01L31/0224 , H01L31/02327 , H01L31/16 , H01L51/5275
摘要： According to various embodiments, an optoelectronic component may be provided, the optoelectronic component including: an electrode structure disposed at least one of over and in a carrier; and a grating structure disposed over the electrode structure, the grating structure including at least a first region and a second region, wherein the first region of the grating structure includes amorphous silicon; and wherein the second region of the grating structure includes a material having a refractive index different from the refractive index of the amorphous silicon.
摘要翻译：根据各种实施例，可以提供光电子部件，所述光电子部件包括：设置在载体中的至少一个和载体中的至少一个的电极结构; 以及设置在所述电极结构上的光栅结构，所述光栅结构至少包括第一区域和第二区域，其中所述光栅结构的所述第一区域包括非晶硅; 并且其中所述光栅结构的第二区域包括具有与所述非晶硅的折射率不同的折射率的材料。

54. 发明授权

US09000520B2 Semiconductor device with an insulating structure for insulating an electrode from a semiconductor body 有权
标题翻译：具有用于将电极与半导体本体绝缘的绝缘结构的半导体器件
公开(公告)号：US09000520B2
公开(公告)日：2015-04-07
申请号：US14177989
申请日：2014-02-11
申请人： Infineon Technologies Dresden GmbH
发明人： Marc Strasser , Karl-Heinz Gebhardt , Ralf Rudolf , Lincoln O'Riain
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/08 , H01L29/10
CPC分类号： H01L29/7816 , H01L29/063 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66681
摘要： A semiconductor device includes an electrode arranged on a main surface of a semiconductor body and an insulating structure insulating the electrode from the semiconductor body. The insulating structure includes in a vertical cross-section a gate dielectric portion forming a first horizontal interface at least with a drift region of the device and having a first maximum vertical extension between the first horizontal interface and the electrode, and a field dielectric portion forming with the drift region second, third and fourth horizontal interfaces. The second through fourth horizontal interfaces are arranged below the main surface. The third horizontal interface is arranged between the second and fourth horizontal interfaces. A second maximum vertical extension is larger than the first maximum vertical extension and a third maximum vertical extension is larger than the second maximum vertical extension. The electrode only partially overlaps the third horizontal interface.
摘要翻译：半导体器件包括布置在半导体主体的主表面上的电极和将电极与半导体本体绝缘的绝缘结构。绝缘结构在垂直截面中包括至少与器件的漂移区形成第一水平界面并且在第一水平界面和电极之间具有第一最大垂直延伸的栅介电部分，以及形成具有漂移区第二，第三和第四水平界面。第二至第四水平接口布置在主表面下方。第三水平界面布置在第二和第四水平界面之间。第二最大垂直延伸大于第一最大垂直延伸，第三最大垂直延伸大于第二最大垂直延伸。电极仅部分地与第三水平界面重叠。

55. 发明授权

US08957490B2 Silicon light trap devices 有权
标题翻译：硅光阱装置
公开(公告)号：US08957490B2
公开(公告)日：2015-02-17
申请号：US13930167
申请日：2013-06-28
申请人： Infineon Technologies Dresden GmbH
发明人： Thoralf Kautzsch
IPC分类号： H01L31/0232 , H01L31/0352
CPC分类号： H01L31/02327 , H01L31/02363 , H01L31/0352 , Y02E10/50
摘要： Embodiments relate to buried structures for silicon devices which can alter light paths and thereby form light traps. Embodiments of the lights traps can couple more light to a photosensitive surface of the device, rather than reflecting the light or absorbing it more deeply within the device, which can increase efficiency, improve device timing and provide other advantages appreciated by those skilled in the art.
摘要翻译：实施例涉及用于硅器件的掩埋结构，其可以改变光路并从而形成光阱。光阱的实施例可以将更多的光耦合到装置的感光表面，而不是反射光或者更深地吸收光，从而可以提高效率，改进装置定时并提供本领域技术人员所理解的其它优点。

56. 发明申请

US20150041811A1 Power Transistor 有权
标题翻译：功率晶体管
公开(公告)号：US20150041811A1
公开(公告)日：2015-02-12
申请号：US13961666
申请日：2013-08-07
申请人： Infineon Technologies Dresden GmbH
发明人： Stefan Tegen
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L27/0886 , H01L29/04 , H01L29/0696 , H01L29/0847 , H01L29/1033 , H01L29/41783 , H01L29/41791 , H01L29/4236 , H01L29/78 , H01L29/7831 , H01L29/785
摘要： A power transistor includes a number of transistor cells. Each transistor cell includes a source region, a drain region, a body region and a gate electrode. Each source region is arranged in a first semiconductor fin of a semiconductor body. Each drain region is at least partially arranged in a second semiconductor fin of the semiconductor body. The second semiconductor fin is spaced from the first semiconductor fin in a first horizontal direction of the semiconductor body. Each gate electrode is arranged in a trench adjacent the first semiconductor fin, is adjacent the body region, and is dielectrically insulated from the body region by a gate dielectric. Each of the first and second semiconductor fins has a width in the first horizontal direction and a length in a second horizontal direction, wherein the length is larger than the width.
摘要翻译：功率晶体管包括多个晶体管单元。每个晶体管单元包括源极区，漏极区，体区和栅电极。每个源极区域布置在半导体本体的第一半导体鳍片中。每个漏极区域至少部分地布置在半导体本体的第二半导体鳍片中。第二半导体鳍片在半导体本体的第一水平方向上与第一半导体鳍片间隔开。每个栅极布置在与第一半导体鳍片相邻的沟槽中，与主体区域相邻，并且通过栅极电介质与体区电介质绝缘。第一和第二半导体翅片中的每一个在第一水平方向上具有宽度，在第二水平方向上具有长度，其中长度大于宽度。

57. 发明申请

US20150035586A1 SOLID-STATE SWITCHING DEVICE HAVING A HIGH-VOLTAGE SWITCHING TRANSISTOR AND A LOW-VOLTAGE DRIVER TRANSISTOR 有权
标题翻译：具有高电压开关晶体管和低电压驱动晶体管的固态开关器件
公开(公告)号：US20150035586A1
公开(公告)日：2015-02-05
申请号：US13957864
申请日：2013-08-02
申请人： Infineon Technologies Dresden GmbH
发明人： Rolf Weis , Anthony Sanders
IPC分类号： H03K17/08
CPC分类号： H03K17/08 , H01L2224/48091 , H01L2224/73265 , H03K17/08104 , H03K17/082 , H03K17/102 , H03K17/687 , H03K17/6871 , H03K2017/0806 , H03K2017/6875 , H01L2924/00014
摘要： According to an embodiment, a solid-state switching device includes a high-voltage switching transistor including a source, a drain and a gate, and being adapted for switching a high voltage on the basis of a switching signal, and a switching driver circuit operationally connected to the high-voltage switching transistor, the switching driver circuit including a low-voltage driver transistor including a source, a drain and a gate, connected in series to the high-voltage switching transistor and being adapted for transferring the switching signal to the high-voltage switching transistor, wherein the high-voltage switching transistor is arranged source-down on top of the drain of the low-voltage driver transistor.
摘要翻译：根据实施例，固态开关装置包括：包括源极，漏极和栅极的高压开关晶体管，并且适于基于开关信号切换高电压;以及开关驱动器电路，连接到高压开关晶体管的开关驱动器电路包括串联连接到高电压开关晶体管的源极，漏极和栅极的低压驱动晶体管，并且适于将开关信号传送到高压开关晶体管，其中高压开关晶体管被排列在低压驱动晶体管的漏极的顶部。

58. 发明申请

US20150008516A1 SEMICONDUCTOR DEVICE WITH BURIED GATE ELECTRODE STRUCTURES 有权
标题翻译：具有栅极电极结构的半导体器件
公开(公告)号：US20150008516A1
公开(公告)日：2015-01-08
申请号：US13934630
申请日：2013-07-03
申请人： Infineon Technologies Dresden GmbH
发明人： Marko Lemke , Rolf Weis , Stefan Tegen
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7813 , H01L21/823437 , H01L21/823487 , H01L29/0696 , H01L29/41758 , H01L29/4236 , H01L29/42376 , H01L29/66553 , H01L29/66621 , H01L29/66734 , H01L29/78
摘要： A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern from a first surface into a semiconductor substrate. An array isolation region including a portion of the semiconductor substrate separates the first and second trench patterns. At least the first trench pattern includes array trenches and a contact trench which is structurally connected with the array trenches. A buried gate electrode structure is provided in a lower section of the first and second trench patterns in a distance to the first surface. A connection plug is provided between the first surface and the gate electrode structure in the contact trench. Gate electrodes of semiconductor switching devices integrated in the same semiconductor portion can be reliably separated and internal gate electrodes can be effectively connected in a cost-effective manner.
摘要翻译：制造半导体器件的方法包括将至少第一沟槽图案和第二沟槽图案从第一表面引入到半导体衬底中。包括半导体衬底的一部分的阵列隔离区域分离第一和第二沟槽图案。至少第一沟槽图形包括阵列沟槽和与阵列沟槽结构连接的接触沟槽。掩模栅电极结构设置在第一和第二沟槽图案的与第一表面相距一定距离的下部。在接触沟槽中的第一表面和栅电极结构之间提供连接插头。集成在同一半导体部分的半导体开关器件的栅极电极可以可靠地分离，并且可以以成本有效的方式有效地连接内部栅极电极。

59. 发明申请

US20150008512A1 Method of Manufacturing a Semiconductor Device with Device Separation Structures and Semiconductor Device 有权
标题翻译：制造具有器件分离结构和半导体器件的半导体器件的方法
公开(公告)号：US20150008512A1
公开(公告)日：2015-01-08
申请号：US13935038
申请日：2013-07-03
申请人： Infineon Technologies Dresden GmbH
发明人： Marko Lemke , Rolf Weis , Stefan Tegen
IPC分类号： H01L29/78 , H01L21/762
CPC分类号： H01L29/0649 , H01L21/761 , H01L21/76224 , H01L21/76232 , H01L21/764 , H01L21/823431 , H01L21/823481 , H01L27/0207 , H01L27/088 , H01L27/0883 , H01L27/0886 , H01L29/4236 , H01L29/66795 , H01L29/7813 , H01L29/7827 , H01L29/7851
摘要： A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern including array trenches from a first surface into a semiconductor substrate, wherein an array isolation portion of the semiconductor substrate separates the first and second trench patterns. A buried gate electrode structure is provided in the first and second trench patterns at a distance to the first surface. In a single etch process, both a device separation trench having a first width is introduced into the array isolation portion and cell separation trenches having at most a second width that is smaller than the first width are introduced into semiconductor fins between the array trenches. Switching devices integrated in the same semiconductor die may be formed in a cost effective way.
摘要翻译：一种制造半导体器件的方法包括将包括阵列沟槽的至少第一沟槽图案和第二沟槽图案从第一表面引入到半导体衬底中，其中半导体衬底的阵列隔离部分分离第一和第二沟槽图案。掩模栅电极结构设置在第一和第二沟槽图案中与第一表面相距一定距离处。在单个蚀刻工艺中，将具有第一宽度的器件分离沟槽引入阵列隔离部分，并且具有至少第二宽度小于第一宽度的细胞分离沟槽被引入到阵列沟槽之间的半导体鳍片中。集成在同一半导体管芯中的开关器件可以以成本有效的方式形成。

60. 发明申请

US20140353852A1 METHOD FOR PROCESSING A CARRIER AND A CARRIER 有权
标题翻译：用于处理载体和载体的方法
公开(公告)号：US20140353852A1
公开(公告)日：2014-12-04
申请号：US13904122
申请日：2013-05-29
申请人： Infineon Technologies Dresden GmbH
发明人： Tarja Hauck , Alessia Sciré , Dieter Kaiser , Andreas Greiner , Morgana Nicolo , Carolin Wetzig , Dietrich Burmeister
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method for processing a carrier may include forming at least one recess structure at least one of over and in the carrier; and annealing the at least one recess structure such that at least one hollow chamber is formed by material of the at least one recess structure, wherein the at least one hollow chamber may form an optical alignment structure.
摘要翻译：一种用于处理载体的方法可以包括：在载体中形成至少一个凹陷结构; 以及退火所述至少一个凹部结构，使得至少一个中空室由所述至少一个凹部结构的材料形成，其中所述至少一个中空室可以形成光学对准结构。

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