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51. 发明申请

US20070241378A1 Method for forming bit line contacts and bit lines during the formation of a semiconductor device, and devices and systems including the bit lines and bit line contacts 有权
标题翻译：在形成半导体器件期间形成位线触点和位线的方法以及包括位线和位线触点的器件和系统
公开(公告)号：US20070241378A1
公开(公告)日：2007-10-18
申请号：US11404209
申请日：2006-04-13
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： H01L29/94
CPC分类号： H01L27/11519 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A method for forming a semiconductor device comprises forming first and second bit lines at different levels. Forming the bit lines at different levels increases processing latitude, particularly the spacing between the bit lines which, with conventional processes, may strain photolithographic limits. A semiconductor device formed using the method, and an electronic system comprising the semiconductor device, are also described.
摘要翻译：一种用于形成半导体器件的方法包括以不同的电平形成第一和第二位线。在不同级别形成位线增加了处理的纬度，特别是位线之间的间距，其与常规工艺可能会使光刻极限变形。还描述了使用该方法形成的半导体器件和包括半导体器件的电子系统。

52. 发明申请

US20070211536A1 Programming a flash memory device 有权
标题翻译：编程闪存设备
公开(公告)号：US20070211536A1
公开(公告)日：2007-09-13
申请号：US11369347
申请日：2006-03-07
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C16/3454
摘要： An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is verified up to a maximum verify voltage. A second verify read operation is then performed after the program/verify operation. The second verify read operation uses a verify voltage that is substantially close to the maximum verify voltage used during the program/verify step.
摘要翻译：在每个编程脉冲之后执行初始验证读操作。验证电压从第一个字线的初始验证电压开始，并且每个被验证到最大验证电压的字线增加。然后在程序/验证操作之后执行第二验证读操作。第二次验证读取操作使用基本上接近程序/验证步骤期间使用的最大验证电压的验证电压。

53. 发明申请

US20070195603A1 Minimizing effects of program disturb in a memory device 有权
标题翻译：最大限度地减少存储设备中程序干扰的影响
公开(公告)号：US20070195603A1
公开(公告)日：2007-08-23
申请号：US11359104
申请日：2006-02-22
申请人： Seiichi Aritome , Todd Marquart
发明人： Seiichi Aritome , Todd Marquart
IPC分类号： G11C11/34 , G11C5/14 , G11C16/06 , G11C16/04
CPC分类号： G11C29/02 , G11C16/04 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C29/021 , G11C29/028
摘要： A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected wordlines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required to successfully program the cells decreases incrementally. Vpass tracks the decrease of the programming voltage.
摘要翻译：耦合到用于编程的单元的所选字线被初始编程电压偏置。与所选择的字线相邻的未选字线被偏置在初始V 。随着存储器件上的编程/擦除周期数量增加，成功编程单元所需的编程电压逐渐减小。 V 跟踪编程电压的减小。

54. 发明申请

US20070195571A1 Bit line coupling 有权
标题翻译：位线耦合
公开(公告)号：US20070195571A1
公开(公告)日：2007-08-23
申请号：US11360873
申请日：2006-02-23
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C7/02
CPC分类号： G11C7/18 , G11C7/02 , G11C7/12 , G11C16/0483 , G11C16/26 , G11C2207/005 , H01L27/115
摘要： Methods and apparatus are provided. In one embodiment, a memory device includes a first bit line selectively coupled to an input of a sensing device through a first multiplexer gate, and a second bit line selectively coupled to the input of the sensing device through a second multiplexer gate. The first bit line is formed at a first vertical layer and is coupled to a first source/drain region of the first multiplexer gate. The input of the sensing device is formed at a second vertical layer different than the first vertical layer and is coupled to a second source/drain region of the first multiplexer gate and a first source/drain region of the second multiplexer gate. The second bit line is formed at the first vertical layer and is coupled to a second source/drain region of the second multiplexer gate.
摘要翻译：提供了方法和装置。在一个实施例中，存储器件包括通过第一多路复用器门选择性地耦合到感测器件的输入的第一位线，以及通过第二多路复用器门选择性地耦合到感测器件输入的第二位线。第一位线形成在第一垂直层并且耦合到第一多路复用器门的第一源/漏区。感测装置的输入形成在不同于第一垂直层的第二垂直层上，并且耦合到第一多路复用器栅极的第二源极/漏极区域和第二多路复用器栅极的第一源极/漏极区域。第二位线形成在第一垂直层处，并且耦合到第二多路复用器门的第二源极/漏极区域。

55. 发明申请

US20070171729A1 MEMORY BLOCK ERASING IN A FLASH MEMORY DEVICE 有权
标题翻译：闪存存储器件中的存储器块擦除
公开(公告)号：US20070171729A1
公开(公告)日：2007-07-26
申请号：US11340093
申请日：2006-01-26
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/344
摘要： The flash memory cell erase operation performs an erase operation at a first erase voltage for a first erase time. An erase verify read operation is then performed for an increasing sensing time period until either all of the memory cells of the block have a threshold voltage that is equal to or greater than an erased threshold voltage or a predetermined quantity of erase verify operations have been performed. The sensing time period for each subsequent verify operation is increased until a maximum sense time is reached. When the memory cells have all been erased, the erase voltage and erase time corresponding to the sensing time period at which the cells passed is used for further erase operations on the memory block.
摘要翻译：闪存单元擦除操作在第一擦除时间的第一擦除电压下执行擦除操作。然后对于增加的感测时间周期执行擦除验证读取操作，直到该块的所有存储单元具有等于或大于擦除的阈值电压的阈值电压或已经执行了预定量的擦除验证操作。每个后续验证操作的感测时间周期增加，直到达到最大感测时间。当存储单元全部被擦除时，对应于单元通过的感测时间周期的擦除电压和擦除时间用于存储块上的进一步的擦除操作。

56. 发明申请

US20070128802A1 NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：US20070128802A1
公开(公告)日：2007-06-07
申请号：US11672376
申请日：2007-02-07
申请人： Seiichi ARITOME
发明人： Seiichi ARITOME
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L21/76224 , H01L27/105 , H01L27/115 , H01L27/11529 , H01L27/11543
摘要： A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction intersecting the first direction. A first conductive material layer is provided at the cross-point of the active area and the wiring trench so that it is insulated from the active area. A second conductive material layer is provided in the wiring trench so that it is insulated from the first conductive material layer. A metal layer is provided in the wiring trench so that it is electrically in contact the second conductive material layer.

57. 发明申请

US20070128778A1 NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20070128778A1
公开(公告)日：2007-06-07
申请号：US11672361
申请日：2007-02-07
申请人： Seiichi ARITOME
发明人： Seiichi ARITOME
IPC分类号： H01L21/84 , H01L21/336 , H01L29/00
CPC分类号： H01L27/11526 , H01L21/76224 , H01L27/105 , H01L27/115 , H01L27/11529 , H01L27/11543
摘要： A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction intersecting the first direction. A first conductive material layer is provided at the cross-point of the active area and the wiring trench so that it is insulated from the active area. A second conductive material layer is provided in the wiring trench so that it is insulated from the first conductive material layer. A metal layer is provided in the wiring trench so that it is electrically in contact the second conductive material layer.
摘要翻译：非易失性半导体存储器包括设置在半导体衬底中的沟槽隔离和设置在半导体衬底上的层间绝缘体。沟槽隔离限定了在半导体衬底处沿第一方向延伸的有源区。层间绝缘体具有沿与第一方向相交的第二方向延伸的布线沟槽。第一导电材料层设置在有源区和布线沟槽的交叉点处，使其与有源区绝缘。第二导电材料层设置在布线沟槽中，使其与第一导电材料层绝缘。金属层设置在布线沟槽中，使其与第二导电材料层电接触。

58. 发明授权

US07212447B2 NAND flash memory cell programming 有权
标题翻译： NAND闪存单元编程
公开(公告)号：US07212447B2
公开(公告)日：2007-05-01
申请号：US11197641
申请日：2005-08-04
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24
摘要： A flash memory device, such as a NAND flash, having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells, the voltage source supplies a pre-charge voltage to the control gates of the floating gate transistor memory cells located in the first addressable block when data is programmed in memory cells of the second addressable block.
摘要翻译：具有布置在第一和第二可寻址块中的浮置晶体管存储单元的阵列的诸如NAND闪存的闪速存储器件。将编程电压提供给浮动栅极晶体管存储单元的控制栅极的电压源，当数据被编程在存储器中时，电压源向位于第一可寻址块中的浮动栅极晶体管存储器单元的控制栅极提供预充电电压第二可寻址块的单元。

59. 发明授权

US07192831B2 Nonvolatile semiconductor memory and manufacturing method thereof 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07192831B2
公开(公告)日：2007-03-20
申请号：US11100492
申请日：2005-04-07
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L21/76224 , H01L27/105 , H01L27/115 , H01L27/11529 , H01L27/11543
摘要： A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction intersecting the first direction. A first conductive material layer is provided at the cross-point of the active area and the wiring trench so that it is insulated from the active area. A second conductive material layer is provided in the wiring trench so that it is insulated from the first conductive material layer. A metal layer is provided in the wiring trench so that it is electrically in contact the second conductive material layer.
摘要翻译：非易失性半导体存储器包括设置在半导体衬底中的沟槽隔离和设置在半导体衬底上的层间绝缘体。沟槽隔离限定了在半导体衬底处沿第一方向延伸的有源区。层间绝缘体具有沿与第一方向相交的第二方向延伸的布线沟槽。第一导电材料层设置在有源区和布线沟槽的交叉点处，使其与有源区绝缘。第二导电材料层设置在布线沟槽中，使其与第一导电材料层绝缘。金属层设置在布线沟槽中，使其与第二导电材料层电接触。

60. 发明申请

US20070047315A1 Program and read trim setting 有权
标题翻译：编程和读取修剪设置
公开(公告)号：US20070047315A1
公开(公告)日：2007-03-01
申请号：US11218851
申请日：2005-09-01
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/102 , G11C16/26
摘要： A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.
摘要翻译：用于在存储器件中设置修剪参数的方法和装置根据观察或测试的编程速度和可靠性提供分配给存储器件部分的多个修整设置。

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