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51. 发明申请

US20130273742A1 METHOD OF FORMING CONNECTION HOLES 有权
标题翻译：形成连接孔的方法
公开(公告)号：US20130273742A1
公开(公告)日：2013-10-17
申请号：US13721070
申请日：2012-12-20
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Yushu YANG , Cheng LI , Yuwen CHEN
IPC分类号： H01L21/306
CPC分类号： H01L21/30604 , H01L21/31116 , H01L21/76816
摘要： The present invention provides a method of forming connection holes. The method utilizes two different gases to perform two etching processes for the interlayer dielectric layer so as to form connection holes. The etching rate of the interlayer dielectric layer in the first etching process using the first etching gas is proportional to the size of the openings which defines the connection hole while the etching rate of the interlayer dielectric layer in the second etching process using the second etching gas is inversely related with size of the openings. According to the present invention, the first etching gas and the second etching gas compensate for each other to eliminate the loading effect, thus the connection holes are formed with almost the same depth. Therefore the damage of the etching stopper layer due to the high etching rate in the larger connection holes can be avoided, which prevents the excessive variation of the connecting resistance and expands the process window.
摘要翻译：本发明提供一种形成连接孔的方法。该方法利用两种不同的气体对层间电介质层进行两次蚀刻处理，形成连接孔。使用第一蚀刻气体的第一蚀刻工艺中的层间电介质层的蚀刻速率与限定连接孔的开口的尺寸成比例，而在使用第二蚀刻气体的第二蚀刻工艺中的层间电介质层的蚀刻速率与开口的尺寸成反比。根据本发明，第一蚀刻气体和第二蚀刻气体彼此补偿以消除负载效应，因此连接孔形成有几乎相同的深度。因此，可以避免由于较大的连接孔中的高蚀刻速率导致的蚀刻阻挡层的损伤，这防止了连接电阻的过度变化并扩大了工艺窗口。

52. 发明申请

US20230128298A1 Electro-Static Discharge Protection Structure and High-Voltage Integrated Circuit 有权
公开(公告)号：US20230128298A1
公开(公告)日：2023-04-27
申请号：US17891413
申请日：2022-08-19
申请人： Shanghai Huali Microelectronics Corporation
发明人： Tianzhi Zhu
IPC分类号： H01L27/02
摘要： The present application discloses an electro-static discharge protection structure, which includes an N-well and a P-well formed in a substrate. Upper parts and middle parts of the N-well and the P-well are isolated by shallow trench isolation (STI), and lower parts adjoin. The upper part of the N-well to form an N-well P-type heavily doped region adjacent to the STI. The upper part of the N-well to form an N-well N-type heavily doped region far away from the STI. The upper part of the P-well forms a P-well P-type heavily doped region adjacent to the STI. The N-well P-type heavily doped region and the N-well N-type heavily doped region are short-circuited to form an anode of the electro-static discharge protection structure. The P-well P-type heavily doped region is used as a cathode of the electro-static discharge protection structure. The present application can realize no snapback effect.

53. 发明授权

US11616121B2 Silicon controlled rectifier and method for making the same 有权
公开(公告)号：US11616121B2
公开(公告)日：2023-03-28
申请号：US17240862
申请日：2021-04-26
申请人： Shanghai Huali Microelectronics Corporation
发明人： Tianzhi Zhu
IPC分类号： H01L29/06 , H01L29/747 , H01L29/74 , H01L29/66
摘要： The present disclosure provides a silicon controlled rectifier and a manufacturing method thereof. The silicon controlled rectifier comprises: an N-type well 60, an upper portion of which is provided with a P-type heavily doped region 20 and an N-type heavily doped region 28; an N-type well 62, an upper portion of which is provided with a P-type heavily doped region 22 and an N-type heavily doped region 26; and a P-type well 70 connecting the N-type well 60 and 62, an upper portion of which is provided with a P-type heavily doped region 24; wherein a first electrode structure is in mirror symmetry with a second electrode structure with respect to the P-type heavily doped region 24, and active regions of the N-type well 60 and 62 are respectively provided between the P-type heavily doped region 24 and each of the N-type heavily doped region 28 and 26.

54. 发明申请

US20220020755A1 SONOS Memory and Method for Making the Same 有权
公开(公告)号：US20220020755A1
公开(公告)日：2022-01-20
申请号：US17352451
申请日：2021-06-21
申请人： Shanghai Huali Microelectronics Corporation
发明人： Xiaoliang Tang , Naoki Tsuji , Haoyu Chen , Hua Shao
IPC分类号： H01L27/1157
摘要： The present application discloses a method for manufacturing a SONOS memory, including: providing a substrate, wherein a first transistor gate of the SONOS memory and a first layer used for forming a second transistor gate are formed on the substrate; forming a patterned second layer on the upper surface of the first layer, wherein the second layer exposes the first layer corresponding to the outer side of the second transistor gate; performing first etching on the first layer exposed by the second layer; removing the second layer; and performing second etching on the first layer to form the second transistor gate. The present application also discloses a SONOS memory. The present application can form a vertical structure outside a selective transistor and a storage transistor, thus forming a vertical side wall in the subsequent process, so as to improve the performance of the device.

55. 发明申请

US20210335775A1 Silicon Controlled Rectifier and Method for Making the Same 有权
公开(公告)号：US20210335775A1
公开(公告)日：2021-10-28
申请号：US17217517
申请日：2021-03-30
申请人： Shanghai Huali Microelectronics Corporation
发明人： Tianzhi Zhu , Guanqun Huang , Haoyu Chen , Hua Shao
IPC分类号： H01L27/02 , H01L29/87 , H01L29/66
摘要： The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region 20 and an N-type heavily doped region 28 forming an anode formed on the upper part of an N-type well 60, a P-type heavily doped region 26 and an N-type heavily doped region 24 forming a cathode formed on the upper part of a P-type well 70, an active region of the N-type well 60 is between the N-type heavily doped region 28 and an interface of the N-type well 60 and the P-type well 70, a STI is provided between the N-type heavily doped region 24 and the interface, the STI is adjacent to the N-type heavily doped region 24, and an active region of the P-type well 70 is provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

56. 发明授权

US11152220B2 Etching method and a semiconductor device 有权
公开(公告)号：US11152220B2
公开(公告)日：2021-10-19
申请号：US16680512
申请日：2019-11-12
申请人： Shanghai Huali Microelectronics Corporation
发明人： Penggang Han , Pengkai Xu
IPC分类号： H01L21/311 , H01L21/308 , H01L21/3105 , H01L21/3213
摘要： The present disclosure relates to the field of semiconductor device etching process, and specifically discloses an etching method and a semiconductor device. The etching method comprises: providing a substrate on which a film layer to be etched is formed; forming a mask layer structure on the film layer to be etched, wherein the mask layer structure includes a dielectric layer formed on an upper surface of the film layer to be etched and an APF layer formed on an upper surface of the dielectric layer; patterning the APF layer; performing a first etching process on the dielectric layer and the film layer to be etched by using the patterned APF layer as a mask to pattern the dielectric layer and partially etch the film layer to be etched; removing the patterned APF layer.

57. 发明申请

US20210312998A1 ONE-TIME PROGRAMMABLE MEMORY AND AN OPERATION METHOD THEREOF 有权
公开(公告)号：US20210312998A1
公开(公告)日：2021-10-07
申请号：US17206631
申请日：2021-03-19
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Ying Yan , Jianming Jin
IPC分类号： G11C17/18 , G11C17/16
摘要： A one-time programmable (OTP) memory cell is disclosed, which comprises an electric fuse structure, an anti-fuse transistor and a word select transistor. One end of the electric fuse structure is electrically connected to a gate of the anti-fuse transistor to form a first port of the OTP memory cell, the other end of the electric fuse structure is electrically connected to a source of the anti-fuse transistor and is connected to a drain of the word select transistor, and a gate and a source of the word select transistor form a second port and a third port of the OTP memory cell respectively. The operation method of the OTP memory cell has the capability of one-time correction, expanding the practicability of the OTP memory cell.

58. 发明申请

US20210305265A1 STACK CAPACITOR, A FLASH MEMORY DEVICE AND A MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20210305265A1
公开(公告)日：2021-09-30
申请号：US17213885
申请日：2021-03-26
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Zhi Tian , Juanjuan LI , Hua SHAO , Haoyu CHEN
IPC分类号： H01L27/11536 , H01L49/02 , H01L27/06 , H01L29/66 , H01L29/788 , H01L27/11539
摘要： The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

59. 发明授权

US11121045B2 Method for detecting ultra-small defect on wafer surface 有权
公开(公告)号：US11121045B2
公开(公告)日：2021-09-14
申请号：US16691180
申请日：2019-11-21
申请人： Shanghai Huali Microelectronics Corporation
发明人： Xianghua Hu , Gaoyu Wang , Guangzhi He , Xiaofang Gu , Qiliang Ni
IPC分类号： G01R31/26 , H01L21/66 , H01L21/02 , H01L21/311
摘要： The present invention provides a method for detecting an ultra-small defect on a wafer surface, film layer having ultra-small defect that causes abnormalities on the surface of the film layer; form a photoresist pattern with a pattern defect; etching the film layer according to the photoresist pattern to form a film layer pattern with an enlarged defect; and scanning the film layer pattern by using a defect scanner to capture the enlarged defect. In this method, enlarging the size of the ultra-fine particle defect through the exposure defocusing principle; or by adding the photomask consisting of the repeating units, using the repetition pattern as the exposure pattern and combing with the repeating cell to cell comparison method, the capture ability of the detection machine is further improved. Therefore, it can be detected by amplifying the defects of ultrafine particles which cannot be detected by conventional methods.

60. 发明授权

US11043504B2 Method for fabricating word lines of NAND memory and NAND memory comprising word lines fabricated by adopting the same 有权
公开(公告)号：US11043504B2
公开(公告)日：2021-06-22
申请号：US16874209
申请日：2020-05-14
申请人： Shanghai Huali Microelectronics Corporation
发明人： Shaokang Yao , Xiaohua Ju , Guanqun Huang
IPC分类号： H01L27/11524 , H01L21/027 , H01L21/768 , H01L27/1157
摘要： Embodiments described herein relate to a method for fabricating word lines of a NAND memory. In the process for fabricating the word lines of the NAND memory, by adding a sacrificial pattern at a position close to a core layer or a sidewall of a select transistor at the edge of the word lines, the actual word line pattern is not at the outermost edge of the pattern, the pattern density of the edge word line pattern is closer to the pattern density of the middle word line pattern, the morphology and size of the edge word line are closer to the morphology and size of the middle area during core layer etching and sidewall etching, and thus the uniformity of the finally etched word lines is improved.

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