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51. 发明授权

US07646039B2 SOI field effect transistor having asymmetric junction leakage 失效
标题翻译：具有不对结结泄漏的SOI场效应晶体管
公开(公告)号：US07646039B2
公开(公告)日：2010-01-12
申请号：US11830972
申请日：2007-07-31
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/7843 , H01L21/26506 , H01L21/26586 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/205 , H01L29/26 , H01L29/267 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66537 , H01L29/6659 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7835 , H01L29/78654
摘要： A source trench and a drain trench are asymmetrically formed in a top semiconductor layer comprising a first semiconductor in a semiconductor substrate. A second semiconductor material having a narrower band gap than the first semiconductor material is deposited in the source trench and the drain trench to form a source side narrow band gap region and a drain side narrow band gap region, respectively. A gate spacer is formed and source and drain regions are formed in the top semiconductor layer. A portion of the boundary between an extended source region and an extended body region is formed in the source side narrow band gap region. Due to the narrower band gap of the second semiconductor material compared to the band gap of the first semiconductor material, charge formed in the extended body region is discharged through the source and floating body effects are reduced or eliminated.
摘要翻译：源极沟槽和漏极沟槽在包括半导体衬底中的第一半导体的顶部半导体层中不对称地形成。在源极沟槽和漏极沟槽中沉积具有比第一半导体材料窄的带隙的第二半导体材料，以分别形成源极窄带隙区域和漏极侧窄带隙区域。形成栅极间隔物，并且在顶部半导体层中形成源区和漏极区。扩展源极区域和延伸体区域之间的边界的一部分形成在源极窄带隙区域中。由于与第一半导体材料的带隙相比，第二半导体材料的带隙较窄，所以形成在扩展体区域中的电荷通过源放电，并且减少或消除浮体效应。

52. 发明申请

US20090242941A1 STRUCTURE AND METHOD FOR MANUFACTURING DEVICE WITH A V-SHAPE CHANNEL NMOSFET 审中-公开
公开(公告)号：US20090242941A1
公开(公告)日：2009-10-01
申请号：US12054738
申请日：2008-03-25
申请人： Huilong Zhu , Zhijiong Luo
发明人： Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823885 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L27/0922 , H01L29/1037 , H01L29/4966 , H01L29/66545 , H01L29/66583 , H01L29/66621
摘要： A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer, such as Ta. Poly-Si is deposited on top of the metal gate layer.

53. 发明授权

US07566609B2 Method of manufacturing a semiconductor structure 失效
标题翻译：制造半导体结构的方法
公开(公告)号：US07566609B2
公开(公告)日：2009-07-28
申请号：US11164568
申请日：2005-11-29
申请人： Zhijiong Luo , Yung Fu Chong , Huilong Zhu
发明人： Zhijiong Luo , Yung Fu Chong , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L21/823864 , H01L29/4975 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要： There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes a gate dielectric layer, conductive layers and an insulating layer. Forming said gate structure includes a step of recessing the conductive layer in the gate structure, and the steps of recessing the conductive layer and forming the recess in the substrate are performed in a single step. There is also provided a FET device.
摘要翻译：提供了一种制造场效应晶体管（FET）的方法，该方法包括以下步骤：在半导体衬底上形成栅极结构，并在衬底中形成凹陷并将第二半导体材料嵌入凹槽中。栅极结构包括栅极电介质层，导电层和绝缘层。形成所述栅极结构包括使栅极结构中的导电层凹陷的步骤，并且在单个步骤中执行使导电层凹陷并且在衬底中形成凹部的步骤。还提供了一种FET器件。

54. 发明授权

US07564081B2 finFET structure with multiply stressed gate electrode 有权
标题翻译：具有多应力栅电极的finFET结构
公开(公告)号：US07564081B2
公开(公告)日：2009-07-21
申请号：US11164621
申请日：2005-11-30
申请人： Huilong Zhu , Zhijiong Luo
发明人： Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/72
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , H01L29/7842
摘要： A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and a second stress which is different than the first stress in a second region located further from the semiconductor fin. The semiconductor fin may also be aligned over a pedestal within the substrate. The semiconductor structure is annealed under desirable stress conditions to obtain an enhancement of semiconductor device performance.
摘要翻译：半导体结构及其制造方法包括位于衬底上的半导体鳍片。栅电极位于半导体鳍上方。栅电极在位于更靠近半导体鳍片的第一区域中具有第一应力，并且在远离半导体鳍片的第二区域中具有与第一应力不同的第二应力。半导体鳍片也可以对准衬底内的基座。半导体结构在期望的应力条件下退火以获得半导体器件性能的增强。

55. 发明授权

US07553709B2 MOSFET with body contacts 失效
标题翻译： MOSFET与主体接触
公开(公告)号：US07553709B2
公开(公告)日：2009-06-30
申请号：US11538560
申请日：2006-10-04
申请人： Huilong Zhu , Zhijiong Luo
发明人： Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/00
CPC分类号： H01L29/78615
摘要： A semiconductor structure includes a metal oxide semiconductor field effect transistor that includes a body contact region that extends from body region located beneath a channel region that separates a pair of source/drain regions within the metal oxide semiconductor field effect transistor. The body contact region is recessed with respect to a surface of the channel region to avoid shorting between a body contact and the source/drain regions.
摘要翻译：半导体结构包括金属氧化物半导体场效应晶体管，其包括从位于金属氧化物半导体场效应晶体管内的一对源极/漏极区域的沟道区域下方的体区延伸的体接触区域。身体接触区域相对于沟道区域的表面凹陷，以避免体接触和源极/漏极区域之间的短路。

56. 发明申请

US20090108324A1 SEMICONDUCTOR FIN BASED NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATION THEREOF 有权
标题翻译：半导体FIN基于非易失性存储器件及其制造方法
公开(公告)号：US20090108324A1
公开(公告)日：2009-04-30
申请号：US11924699
申请日：2007-10-26
申请人： Huilong Zhu , Zhijiong Luo
发明人： Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/788 , H01L21/336 , H01L29/792
CPC分类号： H01L29/785 , H01L21/28282 , H01L29/4234 , H01L29/66795 , H01L29/792
摘要： A semiconductor structure and a method for fabricating the semiconductor structure include a semiconductor fin having a first side and a second side opposite the first side. A first gate dielectric and a charge storage layer are successively layered upon the first side of the semiconductor fin. A second gate dielectric and a gate electrode are layered upon the second side and the charge storage layer. The semiconductor structure comprises a nonvolatile semiconductor device.
摘要翻译：半导体结构和制造半导体结构的方法包括具有第一侧和与第一侧相对的第二侧的半导体鳍。第一栅极电介质和电荷存储层依次层叠在半导体鳍片的第一侧上。第二栅极电介质和栅电极层叠在第二侧和电荷存储层上。半导体结构包括非易失性半导体器件。

57. 发明授权

US07473608B2 N-channel MOSFETs comprising dual stressors, and methods for forming the same 有权
标题翻译：包含双重应力的N沟道MOSFET及其形成方法
公开(公告)号：US07473608B2
公开(公告)日：2009-01-06
申请号：US11840795
申请日：2007-08-17
申请人： Jinghong H. Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
发明人： Jinghong H. Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
IPC分类号： H01L21/22
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/324 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S257/90
摘要： The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.
摘要翻译：本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

58. 发明申请

US20080283934A1 SUBSTANTIALLY L-SHAPED SILICIDE FOR CONTACT AND RELATED METHOD 有权
标题翻译：用于接触的大量L型硅胶和相关方法
公开(公告)号：US20080283934A1
公开(公告)日：2008-11-20
申请号：US12182212
申请日：2008-07-30
申请人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
发明人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
IPC分类号： H01L29/78 , H01L21/44
CPC分类号： H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.
摘要翻译：公开了具有用于接触的大致L形硅化物元件的结构，半导体器件和方法。基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。在一个实施例中，该结构包括基本上为L形的硅化物元件，其包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

59. 发明授权

US07442586B2 SOI substrate and SOI device, and method for forming the same 有权
标题翻译： SOI衬底和SOI器件及其形成方法
公开(公告)号：US07442586B2
公开(公告)日：2008-10-28
申请号：US11308516
申请日：2006-03-31
申请人： Thomas W. Dyer , Zhijiong Luo
发明人： Thomas W. Dyer , Zhijiong Luo
IPC分类号： H01L21/00 , H01L21/84 , H01L21/20 , H01L21/36
CPC分类号： H01L29/0653 , H01L29/66772 , H01L29/78639
摘要： An improved semiconductor-on-insulator (SOI) substrate is provided, which has a substantially planar upper surface and comprises at least first and second patterned buried insulator layers. Specifically, the first patterned buried insulator layer has a first thickness and is located in the SOI substrate at a first depth from the substantially planar upper surface, and the second patterned buried insulator layer has a second, different thickness and is located in the SOI substrate at a second, different depth from the substantially planar upper surface. The first and second patterned buried insulator layers are separated from each other by one or more interlayer gaps, which provide body contacts for the SOI substrate. The SOI substrate of the present invention can be readily formed by a method that includes at least two independent ion implantation steps.
摘要翻译：提供了一种改进的绝缘体上半导体（SOI）衬底，其具有基本平坦的上表面，并且至少包括第一和第二图案化的掩埋绝缘体层。具体地，第一图案化掩埋绝缘体层具有第一厚度并且位于距离基本上平坦的上表面的第一深度处的SOI衬底中，并且第二图案化掩埋绝缘体层具有第二不同厚度并且位于SOI衬底中在距离基本平坦的上表面不同的深度处。第一和第二图案化的掩埋绝缘体层通过一个或多个夹层间隙彼此分开，这为SOI衬底提供体接触。本发明的SOI衬底可以通过包括至少两个独立离子注入步骤的方法容易地形成。

60. 发明授权

US07393751B1 Semiconductor structure including laminated isolation region 有权
标题翻译：半导体结构包括层压隔离区
公开(公告)号：US07393751B1
公开(公告)日：2008-07-01
申请号：US11685457
申请日：2007-03-13
申请人： Zhijiong Luo , Huilong Zhu
发明人： Zhijiong Luo , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/76232 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a related method for fabrication thereof include an isolation region located within an isolation trench within a semiconductor substrate. The isolation region comprises; (1) a lower lying dielectric plug layer recessed within the isolation trench; (2) a U shaped dielectric liner layer located upon the lower lying dielectric plug layer and partially filling the recess; and (3) an upper lying dielectric plug layer located upon the U shaped dielectric liner layer and completely filling the recess. The isolation region provides for sidewall coverage of the isolation trench, thus eliminating some types of leakage paths.
摘要翻译：半导体结构及其相关制造方法包括位于半导体衬底内的隔离沟槽内的隔离区。隔离区域包括：（1）凹陷在所述隔离沟槽内的下部介质插塞层; （2）U形绝缘衬垫层，位于下部介电插塞层上，并部分地填充凹槽; 和（3）位于U形绝缘衬垫层上并完全填充凹槽的上部介电塞层。隔离区域提供隔离沟槽的侧壁覆盖，从而消除一些类型的泄漏路径。

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