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51. 发明授权

US09384050B2 Scheduling method and scheduling system for multi-core processor system 有权
标题翻译：多核处理器系统的调度方法和调度系统
公开(公告)号：US09384050B2
公开(公告)日：2016-07-05
申请号：US14020178
申请日：2013-09-06
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Koji Kurihara , Toshiya Otomo , Naoki Odate
IPC分类号： G06F9/50 , G06F9/46
CPC分类号： G06F9/50 , G06F9/505
摘要： A scheduling method is executed by a first CPU and a second CPU. The scheduling method includes acquiring by the first CPU and when a first application is invoked, a first threshold for executing the first application; transmitting by the first CPU, a first threshold to the second CPU; and giving notification to the first CPU by the second CPU when an execution capability of the second CPU is greater than or equal to the first threshold, the notification indicating that the second CPU can execute the first application. The second CPU does not give notification to the first CPU when the execution capability of the second CPU is less than the first threshold.
摘要翻译：调度方法由第一CPU和第二CPU执行。调度方法包括：由第一CPU获取并调用第一应用时，执行第一应用的第一阈值; 由第一CPU发送第一阈值到第二CPU; 以及当所述第二CPU的执行能力大于或等于所述第一阈值时由所述第二CPU通知所述第一CPU，所述通知指示所述第二CPU可以执行所述第一应用。当第二CPU的执行能力小于第一个阈值时，第二个CPU不向第一个CPU发出通知。

52. 发明申请

US20160182359A1 SYSTEM, NODE, FAILURE DETERMINING SYSTEM, FAILURE DETERMINING METHOD, AND COMPUTER PRODUCT 审中-公开
标题翻译：系统，节点，故障确定系统，故障确定方法和计算机产品
公开(公告)号：US20160182359A1
公开(公告)日：2016-06-23
申请号：US15057476
申请日：2016-03-01
申请人： FUJITSU LIMITED
发明人： Toshiya Otomo , Koichiro Yamashita , Takahisa Suzuki , Hiromasa Yamauchi
IPC分类号： H04L12/733 , H04L12/24
CPC分类号： H04L45/20 , H04L41/06 , H04L41/0677 , H04L45/28 , H04W4/70 , H04W24/04 , H04W40/22 , H04W40/34 , H04W84/18
摘要： A system has a group of nodes that perform multi-hop communication therebetween and a communications apparatus that communicates with a node included in the group of nodes. The node adds to data transmitted by the node, a hop count updated each time the data is transferred by the multi-hop communication and a reference hop count for the data to be transferred from the node to the communications apparatus, and transmits the data. The communications apparatus, when receiving the data, compares the reference hop count and the hop count added to the data, and based on a result of comparison, determines whether failure has occurred at a given node in the group of nodes.
摘要翻译：系统具有在其间执行多跳通信的一组节点和与节点组中包括的节点进行通信的通信装置。节点添加节点发送的数据，每次通过多跳通信传输数据时更新跳数，以及将要从节点传送到通信装置的数据的参考跳计数，并发送数据。通信装置在接收到数据时，比较添加到数据的参考跳计数和跳数，并且基于比较结果来确定在节点组中的给定节点是否发生了故障。

53. 发明申请

US20160179429A1 CONTROLLING MEMORY ACCESS CONFLICT OF THREADS ON MULTI-CORE PROCESSOR WITH SET OF HIGHEST PRIORITY PROCESSOR CORES BASED ON A THRESHOLD VALUE OF ISSUED-INSTRUCTION EFFICIENCY 审中-公开
标题翻译：基于指令效率的阈值控制具有最高优先级处理器线的多核处理器的线程的存储器访问冲突
公开(公告)号：US20160179429A1
公开(公告)日：2016-06-23
申请号：US15057383
申请日：2016-03-01
申请人： FUJITSU LIMITED
发明人： Koichiro YAMASHITA , Hiromasa Yamauchi , Kiyoshi Miyazaki
IPC分类号： G06F3/06
CPC分类号： G06F3/0629 , G06F3/0604 , G06F3/0673 , G06F9/44552 , G06F9/4881 , G06F9/52 , G06F13/1652 , G06F13/18 , G06F13/26
摘要： A multi-core processor system includes multiple cores and memory accessible from the cores, where a given core is configured to detect among the cores, first cores having a highest execution priority level; identify among the detected first cores, a second core that caused access conflict of the memory; and control a third core that is among the cores, excluding the first cores and the identified second core, the third core being controlled to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.
摘要翻译：多核处理器系统包括多个核心和可从核心访问的存储器，其中给定核心被配置为在核心之间检测具有最高执行优先级的第一核心; 在检测到的第一核心之间识别引起存储器的访问冲突的第二核心; 并且控制在核心之内的第三核心，不包括第一核心和所识别的第二核心，第三核心被控制以在发生访问冲突的间隔期间执行给定的间隔时，不访问存储器的线程。

54. 发明授权

US09367326B2 Multiprocessor system and task allocation method 有权
标题翻译：多处理器系统和任务分配方法
公开(公告)号：US09367326B2
公开(公告)日：2016-06-14
申请号：US13718694
申请日：2012-12-18
申请人： FUJITSU LIMITED
发明人： Koji Kurihara , Koichiro Yamashita , Hiromasa Yamauchi , Takahisa Suzuki
IPC分类号： G06F9/46 , G06F9/38 , G06F9/50 , G06F12/08
CPC分类号： G06F9/3877 , G06F9/5027 , G06F12/0831 , G06F2209/503 , G06F2209/509
摘要： A multiprocessor system includes a master processor, at least one slave processor, and a synchronization unit. The master processor has a first flag indicating whether the master processor is in a task activation accepting state and a second flag reflective of a flag of a slave processor, iteratively updates the first flag at a frequency based on the volume of tasks processed by the master processor, and activates a task on the master processor or the slave processor based on the first flag and the second flag. Each slave processor has a third flag indicating whether the slave processor is in the task activation accepting state and iteratively updates the third flag at a frequency based on the volume of tasks processed by the slave processor. Tasks are allocated to the slave processor by the master processor. The synchronization unit synchronizes the third flag and the second flag.
摘要翻译：多处理器系统包括主处理器，至少一个从处理器和同步单元。主处理器具有指示主处理器是处于任务激活接受状态的第一标志和反映从属处理器的标志的第二标志，基于由主设备处理的任务量以一定频率迭代地更新第一标志处理器，并且基于第一标志和第二标志来激活主处理器或从属处理器上的任务。每个从属处理器具有指示从属处理器是否处于任务激活接受状态的第三标志，并且基于由从属处理器处理的任务量以一定频率迭代地更新第三标志。任务由主处理器分配给从属处理器。同步单元同步第三标志和第二标志。

55. 发明授权

US09367311B2 Multi-core processor system, synchronization control system, synchronization control apparatus, information generating method, and computer product 有权
标题翻译：多核处理器系统，同步控制系统，同步控制装置，信息生成方法和计算机产品
公开(公告)号：US09367311B2
公开(公告)日：2016-06-14
申请号：US13765338
申请日：2013-02-12
申请人： FUJITSU LIMITED
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F9/30 , G06F9/38 , G06F9/48 , G06F9/45 , G06F12/08
CPC分类号： G06F9/30043 , G06F8/441 , G06F8/451 , G06F8/458 , G06F9/30123 , G06F9/3828 , G06F9/3834 , G06F9/3851 , G06F9/3891 , G06F9/4856 , G06F12/0831
摘要： A multi-core processor system includes a given core that includes a detecting unit that detects migration of a thread under execution by a synchronization source core to a synchronization destination core in the multi-core processor; an identifying unit that refers to a table identifying a combination of a thread and a register associated with the thread, and identifies a particular register corresponding to the thread for which migration was detected; a generating unit that generates synchronization control information identifying the synchronization destination core and the particular register; and a synchronization controller that, communicably connected to the multi-core processor, acquires from the given core, the synchronization control information, reads in from the particular register of the synchronization source core, a value of the particular register obtainable from the synchronization control information, and writes to the particular register of the synchronization destination core, the value.
摘要翻译：一种多核处理器系统，包括给定的核心，其包括检测单元，该检测单元检测由多核处理器中的同步源核心执行的线程的迁移到同步目的地核心; 标识单元，其指代识别与线程相关联的线程和寄存器的组合的表，并且识别与检测到迁移的线程相对应的特定寄存器; 生成单元，生成识别同步目的地核心和特定寄存器的同步控制信息; 以及可通信地连接到所述多核处理器的同步控制器，从所述给定核心获取所述同步控制信息，从所述同步源核心的特定寄存器读入可从所述同步控制信息获得的所述特定寄存器的值，并写入同步目标内核的特定寄存器，该值。

56. 发明授权

US09348740B2 Memory access controller, multi-core processor system, memory access control method, and computer product 有权
标题翻译：内存访问控制器，多核处理器系统，内存访问控制方法和计算机产品
公开(公告)号：US09348740B2
公开(公告)日：2016-05-24
申请号：US13707306
申请日：2012-12-06
申请人： FUJITSU LIMITED
发明人： Takahisa Suzuki , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara , Kensuke Watanabe
IPC分类号： G06F13/00 , G06F15/16 , G06F12/00 , G06F9/52
CPC分类号： G06F12/00 , G06F9/526 , G06F2209/522
摘要： A memory access controller includes a semiconductor circuit configured to classify into a first group of cores having made an exclusive access request to shared memory and a second group of cores not having made an exclusive access request to the shared memory, multiple cores capable of accessing the shared memory; detect a core having completed the exclusive access among the first group of cores; and send to a core among the first group of cores and standing by for the exclusive access, a notification of release from a standby state, when detecting a core having completed the exclusive access.
摘要翻译：存储器存取控制器包括半导体电路，其被配置为将已经对共享存储器进行独占访问请求的第一组核心和未对共享存储器进行排他访问请求的第二组核心进行分类，共享内存检测完成第一组核心中的独占访问的核心; 并且当检测到完成了独占访问的核心时，发送到第一组核心中的核心，并且等待独占访问，从备用状态释放的通知。

57. 发明授权

US09342451B2 Processor management method 有权
标题翻译：处理器管理方法
公开(公告)号：US09342451B2
公开(公告)日：2016-05-17
申请号：US13972059
申请日：2013-08-21
申请人： FUJITSU LIMITED
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F12/12 , G06F12/02 , G06F11/07 , G06F11/14 , G06F11/20
CPC分类号： G06F12/0284 , G06F11/0742 , G06F11/0751 , G06F11/1484 , G06F11/2025 , G06F11/2035 , G06F11/2097
摘要： A processor management method includes setting a master mechanism in a given processor among multiple processors, where the master mechanism manages the processors; setting a local master mechanism and a virtual master mechanism in each of processors other than the given processor among the processors, where the local master mechanism and the virtual master mechanism manage each of the processors; and notifying by the master mechanism, the processors of an offset value of an address to allow a shared memory managed by the master mechanism to be accessed as a continuous memory by the processors.
摘要翻译：处理器管理方法包括在多个处理器中设置给定处理器中的主机构，其中主机构管理处理器; 在处理器之间的给定处理器之外的每个处理器中设置本地主机构和虚拟主机构，其中本地主机机构和虚拟主机机构管理每个处理器; 并且通过主机构通知处理器将由主机构管理的共享存储器的地址的偏移值作为处理器的连续存储器进行访问。

58. 发明申请

US20160072893A1 COMMUNICATIONS METHOD, SYSTEM, AND COMPUTER PRODUCT 审中-公开
标题翻译：通信方法，系统和计算机产品
公开(公告)号：US20160072893A1
公开(公告)日：2016-03-10
申请号：US14944608
申请日：2015-11-18
申请人： FUJITSU LIMITED
发明人： Takahisa Suzuki , Koichiro Yamashita , Hiromasa Yamauchi , Toshiya Otomo
IPC分类号： H04L29/08 , H04L12/26 , H04L12/46
摘要： A communications method includes transmitting a sensor data collection request to a second network that includes a group of nodes having sensors, the transmitting being performed by a first communications apparatus of plural of communications apparatuses configured to communicate through a first network; and transmitting reception information to the first communications apparatus via the first network, when sensor data is received that is transferred by multihop communication among nodes in the second network and corresponds to the sensor data collection request, the reception information indicating reception of the sensor data, and the transmitting of the reception information being performed by a second communications apparatus of the plural communications apparatuses.
摘要翻译：通信方法包括向包括具有传感器的一组节点的第二网络发送传感器数据收集请求，所述发送由被配置为通过第一网络进行通信的多个通信装置的第一通信装置执行; 以及经由所述第一网络向所述第一通信装置发送接收信息，当接收到通过所述第二网络中的节点之间的多跳通信传送的传感器数据并对应于所述传感器数据收集请求时，所述接收信息指示所述传感器数据的接收，以及由多个通信装置的第二通信装置执行的接收信息的发送。

59. 发明授权

US09223641B2 Multicore processor system, communication control method, and communication computer product 有权
标题翻译：多核处理器系统，通讯控制方式及通讯电脑产品
公开(公告)号：US09223641B2
公开(公告)日：2015-12-29
申请号：US13729854
申请日：2012-12-28
申请人： FUJITSU LIMITED
发明人： Takahisa Suzuki , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara
IPC分类号： G06F9/54 , G06F9/48
CPC分类号： G06F9/542 , G06F9/4843 , G06F9/54
摘要： A multicore processor system is configured to cause among multiple cores, a second core to acquire from a first core that executes a first process, an execution request for a second process and a remaining period from a time of execution of the execution request until an estimated time of completion of the first process; and give notification of a result of the second process from the second core to the first core after an estimated completion time of the first process obtained by adding the remaining period to a start time of the second process.
摘要翻译：多核处理器系统被配置为在多个核心之间引起，第二核心从执行第一进程的第一核心获取第二进程的执行请求以及从执行请求执行的时间到估计的剩余时间段第一个过程的完成时间; 并且在通过将剩余周期添加到第二处理的开始时间而获得的第一处理的估计完成时间之后，将第二处理结果通知给第二核心。

60. 发明申请

US20150019837A1 DATA PROCESSOR 有权
标题翻译：数据处理器
公开(公告)号：US20150019837A1
公开(公告)日：2015-01-15
申请号：US14499334
申请日：2014-09-29
申请人： FUJITSU LIMITED
发明人： Toshiya Otomo , Koichiro Yamashita , Takahisa Suzuki , Hiromasa Yamauchi , Koji Kurihara , Yuta Teranishi
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/30043 , G06F9/30 , G06F9/30036 , G06F9/34 , G06F15/167
摘要： A data processor includes: a plurality of controllers that process data; a program memory that stores a standby instruction and a data processing instruction at a plurality of addresses respectively; and a queue that stores different execution start addresses for the plurality of controllers, wherein after the plurality of controllers sequentially access the queue, the plurality of controllers acquire the different execution start addresses from the queue in an order of the sequential access, start execution of instructions from the acquired different execution start addresses in the program memory, and execute the data processing instruction and execute the standby instruction the number of times different for each of the controllers.
摘要翻译：数据处理器包括：处理数据的多个控制器; 程序存储器，分别在多个地址上存储备用指令和数据处理指令; 以及存储多个控制器的不同执行开始地址的队列，其中，在所述多个控制器顺序访问所述队列之后，所述多个控制器以所述顺序访问的顺序从所述队列获取不同的执行开始地址，开始执行来自程序存储器中获取的不同执行开始地址的指令，并且执行数据处理指令，并且对每个控制器执行不同次数的备用指令。

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