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51. 发明授权

US08912609B2 Low extension resistance III-V compound fin field effect transistor 有权
标题翻译：低延伸电阻III-V复合鳍场效应晶体管
公开(公告)号：US08912609B2
公开(公告)日：2014-12-16
申请号：US13889718
申请日：2013-05-08
申请人： International Business Machines Corporation
发明人： Anirban Basu , Pouya Hashemi
IPC分类号： H01L27/088 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66818 , H01L29/66522 , H01L29/6653 , H01L29/66795 , H01L29/785
摘要： A gate stack including a gate dielectric and a gate electrode is formed over at least one compound semiconductor fin provided on an insulating substrate. The at least one compound semiconductor fin is thinned employing the gate stack as an etch mask. Source/drain extension regions are epitaxially deposited on physically exposed surfaces of the at least one semiconductor fin. A gate spacer is formed around the gate stack. A raised source region and a raised drain region are epitaxially formed on the source/drain extension regions. The source/drain extension regions are self-aligned to sidewalls of the gate stack, and thus ensure a sufficient overlap with the gate electrode. Further, the combination of the source/drain extension regions and the raised source/drain regions provides a low-resistance path to the channel of the field effect transistor.
摘要翻译：在设置在绝缘基板上的至少一个化合物半导体翅片上形成包括栅极电介质和栅电极的栅极堆叠。使用栅极堆叠作为蚀刻掩模来使至少一个化合物半导体鳍薄化。源极/漏极延伸区域外延地沉积在至少一个半导体鳍片的物理暴露表面上。在栅堆叠周围形成栅极间隔物。在源极/漏极延伸区域上外延形成凸起的源极区域和隆起的漏极区域。源极/漏极延伸区域与栅极堆叠的侧壁自对准，从而确保与栅电极的充分重叠。此外，源极/漏极延伸区域和升高的源极/漏极区域的组合提供了到场效应晶体管的沟道的低电阻路径。

52. 发明授权

US08877574B1 Elemental semiconductor material contact for high electron mobility transistor 有权
标题翻译：用于高电子迁移率晶体管的元素半导体材料接触
公开(公告)号：US08877574B1
公开(公告)日：2014-11-04
申请号：US14019717
申请日：2013-09-06
申请人： International Business Machines Corporation
发明人： Anirban Basu , Bahman Hekmatshoartabari , Davood Shahrjerdi
IPC分类号： H01L21/331 , H01L21/337 , H01L21/338 , H01L21/8249 , H01L29/66 , H01L21/283
CPC分类号： H01L29/7786 , H01L21/0272 , H01L21/283 , H01L21/31144 , H01L29/0843 , H01L29/207 , H01L29/267 , H01L29/401 , H01L29/42316 , H01L29/456 , H01L29/475 , H01L29/66431 , H01L29/66462
摘要： Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and the drain trench. Metallization is performed on physically exposed surfaces of the elemental semiconductor material portions in the source trench and the drain trench by depositing a metal and inducing interaction with the metal and the at least one elemental semiconductor material. A metal semiconductor alloy of the metal and the at least one elemental semiconductor material can be performed at a temperature lower than 600° C. to provide a high electron mobility transistor with a well-defined device profile and reliable metallization contacts.
摘要翻译：使用栅电极作为蚀刻掩模来凹陷顶部化合物半导体层的部分以形成源极沟槽和漏极沟槽。采用低温外延工艺在源极沟槽和漏极沟槽中沉积包括至少一种元素半导体材料的半导体材料。通过沉积金属并诱导与金属和至少一种元素半导体材料的相互作用，在源沟槽和漏极沟槽中的元素半导体材料部分的物理暴露的表面上进行金属化。可以在低于600℃的温度下进行金属和至少一种元素半导体材料的金属半导体合金，以提供具有良好限定的器件轮廓和可靠的金属化接触的高电子迁移率晶体管。

53. 发明申请

US20140151757A1 SUBSTRATE-TEMPLATED EPITAXIAL SOURCE/DRAIN CONTACT STRUCTURES 审中-公开
标题翻译：基板模拟外来源/排水接触结构
公开(公告)号：US20140151757A1
公开(公告)日：2014-06-05
申请号：US13692162
申请日：2012-12-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Anirban Basu , Josephine B. Chang , Michael A. Guillorn , Amlan Majumdar
IPC分类号： H01L29/78 , H01L21/76
CPC分类号： H01L21/76 , B82Y40/00 , H01L21/76264 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Single crystalline semiconductor fins are formed on a single crystalline buried insulator layer. After formation of a gate electrode straddling the single crystalline semiconductor fins, selective epitaxy can be performed with a semiconductor material that grows on the single crystalline buried insulator layer to form a contiguous semiconductor material portion. The thickness of the deposited semiconductor material in the contiguous semiconductor material portion can be selected such that sidewalls of the deposited semiconductor material portions do not merge, but are conductively connected to one another via horizontal portions of the deposited semiconductor material that grow directly on a horizontal surface of the single crystalline buried insulator layer. Simultaneous reduction in the contact resistance and parasitic capacitance for a fin field effect transistor can be provided through the contiguous semiconductor material portion and cylindrical contact via structures.
摘要翻译：在单晶埋层绝缘体层上形成单晶半导体散热片。在形成跨越单晶半导体鳍片的栅极电极之后，可以用在单晶掩埋绝缘体层上生长的半导体材料进行选择性外延以形成连续的半导体材料部分。可以选择相邻半导体材料部分中沉积的半导体材料的厚度，使得沉积的半导体材料部分的侧壁不会合并，而是通过直接在水平上生长的沉积的半导体材料的水平部分彼此导电连接单晶埋层绝缘子层的表面。可以通过连续的半导体材料部分和圆柱形接触通孔结构来提供翅片场效应晶体管的接触电阻和寄生电容的同时降低。

54. 发明授权

US10559666B2 Device isolation using preferential oxidation of the bulk substrate 有权
公开(公告)号：US10559666B2
公开(公告)日：2020-02-11
申请号：US16247989
申请日：2019-01-15
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy M. Cohen , Amlan Majumdar , Yu Zhu
IPC分类号： H01L29/66 , H01L29/78 , H01L29/205 , H01L21/762 , H01L21/02
摘要： A structure includes a semiconductor substrate, a semiconductor buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer. The semiconductor material has an oxidation rate different from an oxidation rate of the buffer layer.

55. 发明授权

US10367065B2 Device isolation for III-V substrates 有权
公开(公告)号：US10367065B2
公开(公告)日：2019-07-30
申请号：US16040233
申请日：2018-07-19
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy M. Cohen
IPC分类号： H01L29/205 , H01L21/02 , H01L21/3065 , H01L29/06 , H01L21/306 , H01L21/8234 , H01L21/8252 , H01L29/207 , H01L21/762
摘要： Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.

56. 发明申请

US20180248040A1 CHARGE CARRIER TRANSPORT FACILITATED BY STRAIN 审中-公开
公开(公告)号：US20180248040A1
公开(公告)日：2018-08-30
申请号：US15964765
申请日：2018-04-27
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy M. Cohen
IPC分类号： H01L29/78 , H01L21/02 , H01L29/205 , H01L21/306 , H01L29/04 , H01L29/08 , H01L29/66
摘要： A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second epitaxial semiconductor layer that is lattice-matched with the first semiconductor layer. At least two source/drain regions, which have a second lattice structure, penetrate the second semiconductor layer and contact the first semiconductor layer. A portion of the second semiconductor layer is between the source/drain regions and has a degree of uniaxial strain that is based, at least in part, on a difference between the first lattice structure and the second lattice structure.

57. 发明授权

US10050110B2 Device isolation for III-V substrates 有权
公开(公告)号：US10050110B2
公开(公告)日：2018-08-14
申请号：US15608538
申请日：2017-05-30
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy M. Cohen
IPC分类号： H01L21/20 , H01L29/205 , H01L21/8234 , H01L21/02 , H01L21/3065 , H01L29/06 , H01L29/207 , H01L21/306 , H01L21/8252
摘要： Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.

58. 发明授权

US09997630B2 Charge carrier transport facilitated by strain 有权
公开(公告)号：US09997630B2
公开(公告)日：2018-06-12
申请号：US15338535
申请日：2016-10-31
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy M. Cohen
IPC分类号： H01L29/66 , H01L29/78 , H01L29/205 , H01L29/04 , H01L21/306 , H01L21/02 , H01L29/08 , H01L29/20 , H01L29/423
CPC分类号： H01L29/7848 , H01L21/02392 , H01L21/02546 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/30612 , H01L29/045 , H01L29/0847 , H01L29/20 , H01L29/205 , H01L29/42376 , H01L29/66522 , H01L29/66545 , H01L29/66553 , H01L29/66636
摘要： A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second epitaxial semiconductor layer that is lattice-matched with the first semiconductor layer. At least two source/drain regions, which have a second lattice structure, penetrate the second semiconductor layer and contact the first semiconductor layer. A portion of the second semiconductor layer is between the source/drain regions and has a degree of uniaxial strain that is based, at least in part, on a difference between the first lattice structure and the second lattice structure.

59. 发明授权

US09985113B2 Fabrication process for mitigating external resistance of a multigate device 有权
公开(公告)号：US09985113B2
公开(公告)日：2018-05-29
申请号：US15426566
申请日：2017-02-07
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy Cohen , Amlan Majumdar
IPC分类号： H01L29/66 , H01L29/78 , H01L29/08 , H01L29/201 , H01L29/205
CPC分类号： H01L29/66636 , H01L29/0847 , H01L29/201 , H01L29/205 , H01L29/66522 , H01L29/66795 , H01L29/7784 , H01L29/785 , H01L29/7851
摘要： A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench.

60. 发明申请

US20180130885A1 DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE 审中-公开
公开(公告)号：US20180130885A1
公开(公告)日：2018-05-10
申请号：US15797852
申请日：2017-10-30
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy M. Cohen , Amlan Majumdar , Yu Zhu
IPC分类号： H01L29/205 , H01L29/78 , H01L29/66 , H01L21/762 , H01L21/02
CPC分类号： H01L29/205 , H01L21/02241 , H01L21/762 , H01L29/66795 , H01L29/785
摘要： A method includes providing a structure including a substrate, a buffer layer formed on the substrate and a semiconductor layer formed on the buffer layer, etching the semiconductor layer so as to form a fin and exposing the buffer layer, etching the buffer layer such that a portion of the buffer layer, disposed under the fin, is exposed, and oxidizing the buffer layer and fin so as to form an oxide layer under the fin.

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