专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US08541307B2 Treatment method for reducing particles in dual damascene silicon nitride process 有权
标题翻译：双镶嵌氮化硅工艺中还原颗粒的处理方法
公开(公告)号：US08541307B2
公开(公告)日：2013-09-24
申请号：US13339400
申请日：2011-12-29
申请人： Meimei Gu , Duoyuan Hou , Jun Xu , Ke Wang
发明人： Meimei Gu , Duoyuan Hou , Jun Xu , Ke Wang
IPC分类号： H01L21/44
CPC分类号： H01L21/76883 , H01L21/02074 , H01L21/0217 , H01L21/02301 , H01L21/02315 , H01L21/76834
摘要： A treatment method for reducing particles in a Dual Damascene Silicon Nitride (DDSN) process, including the following steps: forming a seed layer of copper on a silicon wafer; depositing a deposition layer of copper to cover the seed layer of copper; planarizing the deposition layer of copper; providing the silicon wafer into a reaction chamber and performing a pre-treatment on a surface of the deposition layer of copper using NH3 gas under a plasma condition so as to reduce copper oxide (CuO) to copper (Cu) formed on the deposition layer of copper; in the reaction chamber, generating an etching block layer on the deposition layer of copper using a DDSN deposition process; cleaning the reaction chamber using NF3 gas; and directing N2O gas into the reaction chamber and removing the remaining hydrogen (H) and fluorine (F) in the reaction chamber using the N2O gas under the plasma condition.
摘要翻译：一种用于减少双镶嵌氮化硅（DDSN）工艺中的颗粒的处理方法，包括以下步骤：在硅晶片上形成铜种子层; 沉积铜沉积层以覆盖铜的籽晶层; 平坦化铜的沉积层; 将硅晶片提供到反应室中，并且在等离子体条件下使用NH 3气体在铜的沉积层的表面上进行预处理，以将氧化铜（CuO）还原成形成在沉积层上的铜（Cu）铜; 在反应室中，使用DDSN沉积工艺在铜的沉积层上产生蚀刻阻挡层; 使用NF3气体清洗反应室; 并在等离子体条件下使用N2O气体将N 2 O气体引入反应室并除去反应室中剩余的氢（H）和氟（F）。

52. 发明授权

US08518825B1 Method to manufacture trench-first copper interconnection 有权
标题翻译：制造沟槽第一铜互连的方法
公开(公告)号：US08518825B1
公开(公告)日：2013-08-27
申请号：US13726532
申请日：2012-12-24
申请人： Zhibiao Mao
发明人： Zhibiao Mao
IPC分类号： H01L21/44 , H01L21/00 , H01L21/4763 , H01L21/31 , H01L21/469 , H01L23/48 , H01L23/52
CPC分类号： H01L21/0273 , H01L21/31144 , H01L21/76811 , H01L21/76816 , H01L2924/0002
摘要： The present invention relates to manufacturing technology of damascene copper interconnection in the semiconductor manufacturing field, and especially relates to a method to manufacture by trench-first copper interconnection. The method to manufacture trench-first copper interconnection forms metal trench and VIA hole structures in the photoresist which can form a hard mask through exposure and development processes, and then forms metal interconnection lines via etching metal trench and VIA hole in one etch process. The above method replaces the existing.
摘要翻译：本发明涉及半导体制造领域的镶嵌铜互连的制造技术，特别涉及通过沟槽第一铜互连制造的方法。制造沟槽第一铜互连的方法在光致抗蚀剂中形成金属沟槽和VIA孔结构，其可以通过曝光和显影工艺形成硬掩模，然后在一个蚀刻工艺中通过蚀刻金属沟槽和VIA孔形成金属互连线。上述方法取而代之。

53. 发明授权

US08426288B2 Method for improving capacitance uniformity in a MIM device 有权
标题翻译：用于改善MIM器件中的电容均匀性的方法
公开(公告)号：US08426288B2
公开(公告)日：2013-04-23
申请号：US13339406
申请日：2011-12-29
申请人： Qiang Xu , Wenguang Zhang , Chunsheng Zheng , Yuwen Chen
发明人： Qiang Xu , Wenguang Zhang , Chunsheng Zheng , Yuwen Chen
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , C23C16/345 , C23C16/45523 , C23C16/505 , C23C16/56
摘要： A method for improving capacitance uniformity in a MIM device, mainly for the purpose of improving uniformity of a thin film within the MIM device, includes eight steps in order and step S2-step S6 may be repeated for several times as needed. According to the method for improving capacitance uniformity in a MIM device of the present invention, a certain quantity of defects in the thin film are removed by means of several times of deposition/plasma processes based on the current PECVD, and uniformity of the deposited thin film is increased, thereby improving uniformity in wet etching rate of the thin film and further improving capacitance uniformity in the MIM device.
摘要翻译：主要用于提高MIM器件内的薄膜均匀性的MIM器件中的电容均匀性的改善方法包括8个步骤，并且步骤S2的步骤S6可根据需要重复多次。根据本发明的MIM器件中的电容均匀性的提高方法，通过基于当前PECVD的多次沉积/等离子体处理，去除薄膜中的一定量的缺陷，并且沉积的薄膜膜增加，从而提高了薄膜的湿蚀刻速度的均匀性，并且进一步提高了MIM器件中的电容均匀性。

54. 发明申请

US20120276820A1 Method for Adjusting Metal Polishing Rate and Reducing Defects Arisen in a Polishing Process 审中-公开
标题翻译：调整金属抛光速率和减少抛光过程中出现的缺陷的方法
公开(公告)号：US20120276820A1
公开(公告)日：2012-11-01
申请号：US13339538
申请日：2011-12-29
申请人： Shoulong Zhang , Yingying Bai , Yuwen Chen
发明人： Shoulong Zhang , Yingying Bai , Yuwen Chen
IPC分类号： B24B1/00
CPC分类号： H01L21/7684 , B24B37/046 , B24B37/22 , B24B37/24 , H01L21/32125
摘要： The invention discloses a method for adjusting metal polishing rate and reducing defects arisen in a polishing process, in which a electric conduction system is additionally provided to a polishing apparatus to electrify the polishing fluid; in the polishing process, the polishing fluid flows through the polishing pad and the wafer to be polished, such that the polished metal surface of the wafer is electrically charged so as to control the oxidation of the polished metal surface of the wafer. The invention has solved the problem that the dishing and erosion defects are prone to be formed in the existing polishing process, the potential of the polishing fluid is changed by means of the additional electric conduction system and thus the polishing rate of the polished metal is controlled so as to reduce the dishing and erosion defects occurred in the polishing process.
摘要翻译：本发明公开了一种用于调整金属抛光速率并减少在抛光工艺中产生的缺陷的方法，其中将电传导系统附加地提供给抛光装置以使抛光液带电; 在抛光过程中，抛光液流过待研磨的抛光垫和晶片，使得抛光的晶片的金属表面被带电，以便控制晶片抛光的金属表面的氧化。本发明解决了在现有的抛光工艺中容易形成凹陷和侵蚀缺陷的问题，通过附加的导电系统改变抛光液的电位，从而控制抛光金属的抛光速度以减少抛光过程中发生的凹陷和侵蚀缺陷。

55. 发明授权

US11545482B2 No-snapback silicon controlled rectifier and method for making the same 有权
公开(公告)号：US11545482B2
公开(公告)日：2023-01-03
申请号：US17217644
申请日：2021-03-30
申请人： Shanghai Huali Microelectronics Corporation
发明人： Tianzhi Zhu , Guanqun Huang , Haoyu Chen , Hua Shao
IPC分类号： H01L29/87 , H01L29/06 , H01L27/02 , H01L21/8228
摘要： The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region 20 and an N-type lightly doped region 28 forming an anode formed on the upper part of an N-type well 60, a P-type heavily doped region 26 and an N-type heavily doped region 24 forming a cathode formed on the upper part of a P-type well 70, an active region of the N-type well 60 is between the N-type lightly doped region 28 and an interface of the N-type well 60 and the P-type well 70, a STI is provided between the N-type heavily doped region 24 and the interface, the STI is adjacent to the N-type heavily doped region 24, and an active region of the P-type well 70 is provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

56. 发明授权

US11462627B2 Manufacturing method for a semiconductor device 有权
公开(公告)号：US11462627B2
公开(公告)日：2022-10-04
申请号：US17244620
申请日：2021-04-29
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Xiang Peng , Haoyu Chen , Qiwei Wang
IPC分类号： H01L29/66
摘要： The present invention provides a manufacturing method for a semiconductor memory device. The method comprises: providing a substrate, wherein a gate structure of a memory transistor is formed on a memory area of the substrate, and a first layer used for forming a gate structure of a peripheral transistor is formed on a peripheral area of the substrate; performing lightly doped drain ion implantation on an upper part of a portion, on two sides of the gate structure of the memory transistor, of the memory area of the substrate by applying the first layer as a mask of the peripheral area; and etching the first layer to form the gate structure of the peripheral transistor. According to the present invention, an ion diffusion degree of source and drain electrodes of the memory area may be effectively increased, and the uniformity of a memory cell device is improved.

57. 发明授权

US11315942B2 Nonvolatile memory device having a memory-transistor gate-electrode provided with a charge-trapping gate-dielectric layer and two sidewall select-transistor gate-electrodes 有权
公开(公告)号：US11315942B2
公开(公告)日：2022-04-26
申请号：US16666418
申请日：2019-10-29
申请人： Shanghai Huali Microelectronics Corporation
发明人： Xiaoliang Tang , Guanglong Chen , Naoki Tsuji , Hua Shao
IPC分类号： H01L27/11568 , H01L21/28 , H01L21/02 , H01L21/265 , H01L21/762 , H01L27/02 , H01L27/12 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/792 , H01L27/1157 , H01L29/78 , G11C16/04
摘要： The present disclosure provides a SONOS memory structure and a manufacturing method therefor. The SONOS memory structure including a substrate and a select transistor gate and a memory transistor gate formed on the substrate, wherein the substrate is a composite substrate including a base silicon layer, a buried oxide layer and a surface silicon layer, wherein the upper portion of the base silicon layer has a memory transistor well region formed therein; the select transistor gate and the memory transistor gate are formed on the surface silicon layer; the select transistor gate comprises a first select transistor gate and a second select transistor gate, the first select transistor gate and the second select transistor gate are respectively located at two sides of the memory transistor gate, and are electrically isolated from the memory transistor gate by first spacers on both sides of the memory transistor gate.

58. 发明授权

US11302867B2 Method of making resistive structure of RRAM 有权
公开(公告)号：US11302867B2
公开(公告)日：2022-04-12
申请号：US16850993
申请日：2020-04-16
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Youqing Tang , Zhigang Zhang
IPC分类号： H01L45/00
摘要： A method for making an RRAM resistive structure includes, step 1, forming a via structure, which includes depositing an ultra-low dielectric constant material layer on a substrate, depositing a copper layer on the ultra-low dielectric constant material layer, depositing a carbon-containing silicon nitride layer, and patterning a via in the carbon-containing silicon nitride layer. step 2, filling the via structure with a TaN layer, followed by planarizing a surface of the via structure without dishing; step 3, forming a first TiN layer on the TaN-filled via structure; and step 4, forming an RRAM resistive structure stack having layers of TaOx, Ta2O5, Ta, and a second TiN from bottom to top on the first TiN layer, and step 5, patterning the RRAM resistive structure stack the first TiN layer over the TaN-filled via structure to form the RRAM resistive structure.

59. 发明申请

US20220069145A1 Method for Forming Doped Epitaxial Layer of Contact Image Sensor 有权
公开(公告)号：US20220069145A1
公开(公告)日：2022-03-03
申请号：US17142431
申请日：2021-01-06
申请人： Shanghai Huali Microelectronics Corporation
发明人： Chenchen Qiu , Jun Qian , Chang Sun , Zhengying Wei
IPC分类号： H01L31/0352 , H01L27/146 , H01L31/18
摘要： The disclosure discloses a method for forming a doped epitaxial layer of contact image sensor. Epitaxial growth is performed in times. After each time of epitaxial growth, trench isolation and ion implantation are performed to form deep and shallow trench isolation running through a large-thickness doped epitaxial layer. Through cyclic operation of epitaxial growth, trench isolation and ion implantation, the photoresist and hard mask required at each time do not need to be too thick. In the process of trench isolation and ion implantation, the photoresist and etching morphologies are good, such that the lag problem of the prepared contact image sensor is improved. By forming the large-thickness doped epitaxial layer by adopting the method for forming the doped epitaxial layer of the contact image sensor, a high-performance contact image sensor applicable to high quantum efficiency, small pixel size and near infrared/infrared can be prepared.

60. 发明授权

US11204613B2 LDO circuit device and overcurrent protection circuit thereof 有权
公开(公告)号：US11204613B2
公开(公告)日：2021-12-21
申请号：US16800614
申请日：2020-02-25
申请人： Shanghai Huali Microelectronics Corporation
发明人： Ning Zhang , Jingping Gu
IPC分类号： G05F1/573 , G05F1/46 , G05F1/575
摘要： Embodiments described herein relate to an LDO circuit device and overcurrent protection circuit of an LDO circuit. An overcurrent protection circuit is added to an LDO circuit to process an output current signal of the LDO circuit. When the output current signal of the LDO circuit increases, a voltage of a gate drive signal of a power switch in the LDO circuit is increased through adjustment performed by the overcurrent protection circuit, thereby declining the current capability of the power switch in the LDO circuit and restricting an output current thereof from continuing to increase. After feedback regulation, the output current of the LDO finally reaches to a stable value.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式