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51. 发明申请

US20150043114A1 JUNCTION-LESS INSULATED GATE CURRENT LIMITER DEVICE 有权
标题翻译：无连接绝缘栅极电流限制器件
公开(公告)号：US20150043114A1
公开(公告)日：2015-02-12
申请号：US14454435
申请日：2014-08-07
申请人： Fairchild Semiconductor Corporation
发明人： Tirthajyoti SARKAR , Adrian MIKOLAJCZAK , Ihsiu HO , Ashok CHALLA
IPC分类号： H01L27/02 , H01L29/772 , H02H9/04 , H01L29/40
CPC分类号： H01L27/027 , H01L27/0266 , H01L27/0288 , H01L29/1608 , H01L29/20 , H01L29/407 , H01L29/408 , H01L29/6606 , H01L29/66166 , H01L29/772 , H01L29/8605 , H01L29/861
摘要： In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.
摘要翻译：在一个一般方面，装置可以包括半导体衬底和限定在半导体衬底内并具有沿着垂直轴线对准的深度，沿着纵向轴线对准的长度和沿着水平轴线对齐的宽度的沟槽。该设备包括设置在沟槽内的电介质和设置在电介质内并通过电介质与半导体衬底绝缘的电极。半导体衬底可以具有垂直且与沟槽相邻的部分，并且半导体衬底的部分可以具有沿沟槽的整个深度连续的导电类型。该装置被偏置到常开状态。

52. 发明授权

US08941175B2 Power array with staggered arrangement for improving on-resistance and safe operating area 有权
标题翻译：功率阵列具有交错布置，用于改善导通电阻和安全工作区域
公开(公告)号：US08941175B2
公开(公告)日：2015-01-27
申请号：US13918994
申请日：2013-06-17
申请人： United Microelectronics Corp.
发明人： Wei-Lin Chen , Ke-Feng Lin , Chiu-Ling Lee , Chiu-Te Lee , Chih-Chung Wang , Hsuan-Po Liao
IPC分类号： H01L29/06 , H01L29/772 , H01L27/088 , H01L27/092
CPC分类号： H01L29/7816 , H01L27/0207 , H01L29/0692 , H01L29/0696 , H01L29/4238 , H01L29/78
摘要： A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.
摘要翻译：提供具有交错布置的用于改善设备的导通电阻和安全操作区域的功率阵列。每个功率阵列包括两行或更多行，具有沿行排列的多个并行设备单元。每个器件单元包括源极区域，漏极区域和设置在源极区域和漏极区域之间的栅极，其中每个漏极区域在相邻行的相邻漏极区域沿行方向偏移。

53. 发明申请

US20150008445A1 III-Nitride Device and FET in a Package 有权
标题翻译： III-Nitride器件和封装中的FET
公开(公告)号：US20150008445A1
公开(公告)日：2015-01-08
申请号：US14496140
申请日：2014-09-25
申请人： International Rectifier Corporation
发明人： Heny Lin , Jason Zhang , Alberto Guerra
IPC分类号： H01L25/07 , H01L29/16 , H01L29/772 , H01L23/00 , H01L29/20
CPC分类号： H01L25/074 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/69 , H01L24/72 , H01L24/73 , H01L29/16 , H01L29/2003 , H01L29/772 , H01L29/778 , H01L2224/0603 , H01L2224/2919 , H01L2224/32145 , H01L2224/32245 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48145 , H01L2224/48247 , H01L2224/49111 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06568 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/10253 , H01L2924/10323 , H01L2924/1033 , H01L2924/10334 , H01L2924/10344 , H01L2924/10346 , H01L2924/1306 , H01L2924/15787 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.
摘要翻译：一个示例性的公开的实施例包括三端子堆叠管芯封装，其包括层叠在III族氮化物晶体管的顶部的诸如硅PET的场效应晶体管（PET），使得PET的漏极位于电耦合到 III族氮化物晶体管的源极。封装的第一端子耦合到FET的栅极，封装的第二端子耦合到III族氮化物晶体管的漏极。封装的第三端子耦合到FET的源极。以这种方式，诸如级联开关的器件可以以堆叠的管芯形式被封装，从而与常规封装相比，减小了寄生电感和电阻，改善的散热，更小的外形尺寸和更低的制造成本。

54. 发明授权

US08896067B2 Method of forming finFET of variable channel width 有权
标题翻译：形成可变通道宽度的finFET的方法
公开(公告)号：US08896067B2
公开(公告)日：2014-11-25
申请号：US13736111
申请日：2013-01-08
申请人： International Business Machines Corporation
发明人： Marc Adam Bergendahl , David Vaclav Horak , Shom Ponoth , Chih-Chao Yang , Charles William Koburger, III
IPC分类号： H01L29/772 , H01L29/66 , H01L27/088
CPC分类号： H01L27/0886 , H01L21/823431 , H01L29/785
摘要： Embodiments of present invention provide a method of forming a first and a second group of fins on a substrate; covering a top first portion of the first and second groups of fins with a first dielectric material; covering a bottom second portion of the first and second groups of fins with a second dielectric material, the bottom second portion of the first group and the second group of fins having a same height; exposing a middle third portion of the first and second groups of fins to an oxidizing environment to create an oxide section that separates the top first portion from the bottom second portion of the first and second groups of fins; and forming one or more fin-type field-effect-transistors (FinFETs) using the top first portion of the first and second groups of fins as fins under gates of the one or more FinFETs.
摘要翻译：本发明的实施例提供一种在基板上形成第一组翅片和第二组翅片的方法; 用第一介电材料覆盖第一和第二组翅片的顶部第一部分; 用第二电介质材料覆盖第一和第二组翅片的底部第二部分，第一组的底部第二部分和具有相同高度的第二组翅片; 将第一组翅片和第二组翅片的中间第三部分暴露于氧化环境以产生将顶部第一部分与第一组翅片和第二组鳍片的底部第二部分分离的氧化物部分; 以及使用所述第一和第二组翅片的顶部第一部分在所述一个或多个FinFET的栅极下形成翅片形成一个或多个鳍状场效应晶体管（FinFET）。

55. 发明授权

US08865551B2 Reducing the inversion oxide thickness of a high-k stack fabricated on high mobility semiconductor material 有权
标题翻译：降低在高迁移率半导体材料上制造的高k叠层的反转氧化物厚度
公开(公告)号：US08865551B2
公开(公告)日：2014-10-21
申请号：US13536764
申请日：2012-06-28
申请人： Takashi Ando , Martin M. Frank , Vijay Narayanan
发明人： Takashi Ando , Martin M. Frank , Vijay Narayanan
IPC分类号： H01L29/772 , H01L29/78 , H01L21/8234
CPC分类号： H01L21/823462 , H01L21/28255 , H01L21/28264 , H01L21/82345 , H01L29/1054 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66477 , H01L29/665 , H01L29/66522
摘要： A high mobility semiconductor layer is formed over a semiconductor substrate. An interfacial oxide layer is formed over the high mobility semiconductor layer. A high dielectric constant (high-k) dielectric layer is formed over the interfacial oxide layer. A stack is formed over the high-k dielectric layer. The stack comprises a lower metal layer, a scavenging metal layer comprising a scavenging metal, and an upper metal layer formed on the scavenging metal layer. A Gibbs free energy change of a chemical reaction, in which an atom constituting the high mobility semiconductor layer that directly contacts the interfacial oxide layer combines with a metal oxide material comprising the scavenging metal and oxygen to form the scavenging metal in elemental form and oxide of the atom constituting the high mobility semiconductor layer that directly contacts the interfacial oxide layer, is positive. A gate electrode and a gate dielectric are formed.
摘要翻译：在半导体衬底上形成高迁移率半导体层。在高迁移率半导体层上形成界面氧化物层。在界面氧化物层上形成高介电常数（high-k）介电层。堆叠形成在高k电介质层上。堆叠包括下金属层，包含清除金属的清除金属层和形成在扫气金属层上的上金属层。化学反应的吉布斯自由能变化，其中构成直接与界面氧化物层接触的高迁移率半导体层的原子与包含清除金属和氧的金属氧化物材料结合，以形成元素形式的清除金属和氧化物构成与界面氧化物层直接接触的高迁移率半导体层的原子为正。形成栅极电极和栅极电介质。

56. 发明授权

US08853041B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08853041B2
公开(公告)日：2014-10-07
申请号：US14182257
申请日：2014-02-17
申请人： United Microelectronics Corp.
发明人： Ching-Wen Hung
IPC分类号： H01L29/66 , H01L29/51 , H01L21/8238 , H01L29/772 , H01L29/417 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/823807 , H01L21/823814 , H01L29/41783 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/772 , H01L29/7848
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a region; forming a gate structure on the region of the substrate; forming a raised epitaxial layer in the substrate adjacent to two sides of the gate structure; covering a dielectric layer on the gate structure and the raised epitaxial layer; and using a planarizing process to partially remove the dielectric layer and the gate structure such that the surface of the gate structure is even with the surface of the raised epitaxial layer.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：提供具有区域的衬底; 在所述基板的区域上形成栅极结构; 在所述衬底中邻近所述栅极结构的两侧形成凸起的外延层; 覆盖栅极结构和凸起的外延层上的介电层; 并且使用平坦化工艺来部分去除电介质层和栅极结构，使得栅极结构的表面与凸起的外延层的表面均匀。

57. 发明授权

US08835316B2 Transistor with primary and semiconductor spacer, method for manufacturing transistor, and semiconductor chip comprising the transistor 有权
标题翻译：具有初级和半导体衬垫的晶体管，晶体管的制造方法和包括晶体管的半导体芯片
公开(公告)号：US08835316B2
公开(公告)日：2014-09-16
申请号：US13378997
申请日：2011-08-09
申请人： Haizhou Yin , Jun Luo , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Jun Luo , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/772 , H01L21/3213 , H01L21/768 , H01L29/78 , H01L29/66 , H01L29/417 , H01L21/285
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/32139 , H01L21/76897 , H01L29/41775 , H01L29/665 , H01L29/6659
摘要： The disclosure provides a transistor, a method for manufacturing the transistor, and a semiconductor chip comprising the transistor. The transistor comprises: an active area, a gate stack, a primary spacer, and source/drain regions, wherein the active area is on a semiconductor substrate; the gate stack, the primary spacer, and the source/drain regions are on the active area; the primary spacer surrounds the gate stack; the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer. Wherein the transistor further comprises: a silicide spacer, wherein the silicide spacer is located at opposite sides of the primary spacer, and a dielectric material is filled between the two ends of the silicide spacer in the width direction of the gate stack, so as to isolate the source/drain regions from each other.
摘要翻译：本发明提供一种晶体管，一种晶体管的制造方法和一种包括该晶体管的半导体芯片。晶体管包括：有源区，栅极堆叠，初级间隔物和源/漏区，其中有源区在半导体衬底上; 栅极堆叠，初级间隔物和源极/漏极区域在有源区域上; 主要间隔物围绕栅极堆叠; 源极/漏极区域被嵌入有源区域中并且与主隔板的相对侧自对准。其中，所述晶体管还包括：硅化物间隔物，其中所述硅化物间隔物位于所述主间隔物的相对侧，并且电介质材料填充在所述硅化物间隔物的所述栅堆叠的宽度方向的两端之间，以便将源极/漏极区彼此隔离。

58. 发明授权

US08796788B2 Semiconductor devices with strained source/drain structures 有权
标题翻译：具有应变源/漏结构的半导体器件
公开(公告)号：US08796788B2
公开(公告)日：2014-08-05
申请号：US13009322
申请日：2011-01-19
申请人： Tsz-Mei Kwok , Hsueh-Chang Sung , Kuan-Yu Chen , Hsien-Hsin Lin
发明人： Tsz-Mei Kwok , Hsueh-Chang Sung , Kuan-Yu Chen , Hsien-Hsin Lin
IPC分类号： H01L29/772
CPC分类号： H01L29/6659 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved source/drain features in the semiconductor device. Semiconductor devices with the improved source/drain features may prevent or reduce defects and achieve high strain effect resulting from epi layers. In an embodiment, the source/drain features comprises a second portion surrounding a first portion, and a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions.
摘要翻译：公开了一种用于制造集成电路器件的集成电路器件和方法。所公开的方法提供了用于在半导体器件中形成改进的源极/漏极特征的处理。具有改善的源极/漏极特征的半导体器件可以防止或减少缺陷并实现由epi层产生的高应变效应。在一个实施例中，源极/漏极特征包括围绕第一部分的第二部分和在第二部分和半导体衬底之间的第三部分，其中第二部分具有不同于第一和第三部分的组成。

59. 发明授权

US08796080B2 Methods of epitaxially forming materials on transistor devices 有权
标题翻译：在晶体管器件上外延形成材料的方法
公开(公告)号：US08796080B2
公开(公告)日：2014-08-05
申请号：US13287466
申请日：2011-11-02
申请人： Stephan Kronholz , Hans-Juergen Thees , Peter Javorka
发明人： Stephan Kronholz , Hans-Juergen Thees , Peter Javorka
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/76232 , H01L29/1054 , H01L29/6659 , H01L29/66651 , H01L29/7834 , H01L29/7849
摘要： Disclosed herein are various methods of epitaxially forming materials on transistor devices. In one example, the method includes forming an isolation region in a semiconducting substrate that defines an active area, performing a heating process on the active area to cause an upper surface of the active area to become a curved surface and performing an etching process on the active area to define a recess having a curved bottom surface. The method further includes the steps of forming a channel semiconductor material in the recess with a curved upper surface and forming a gate structure for a transistor above the curved upper surface of the channel semiconductor material.
摘要翻译：本文公开了在晶体管器件上外延形成材料的各种方法。在一个示例中，该方法包括在限定有源区域的半导体衬底中形成隔离区域，在有源区域上执行加热处理，以使有源区域的上表面变成曲面，并且对活动区域以限定具有弯曲底面的凹部。该方法还包括以下步骤：在具有弯曲的上表面的凹槽中形成沟道半导体材料，并在通道半导体材料的弯曲上表面上形成用于晶体管的栅极结构。

60. 发明授权

US08772148B1 Metal gate transistors and fabrication method thereof 有权
标题翻译：金属栅晶体管及其制造方法
公开(公告)号：US08772148B1
公开(公告)日：2014-07-08
申请号：US14030026
申请日：2013-09-18
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Xinpeng Wang , Qiyang He
IPC分类号： H01L29/772
CPC分类号： H01L29/772 , H01L21/823456 , H01L21/823468 , H01L29/517 , H01L29/66545 , H01L29/6656
摘要： A method is provided for fabricating a metal gate transistor. The method includes providing a semiconductor substrate; and forming a dielectric layer on the semiconductor substrate. The method also includes forming at least one dummy gate on the dielectric layer; and forming a first sidewall spacer around the dummy gate. Further, the method includes forming a gate dielectric layer with sidewalls protruding from sidewalls of the dummy gate and vertical to the semiconductor substrate by etching the dielectric layer using the first sidewall spacer and the dummy gate as an etching mask; and removing the dummy gate to form a trench. Further, the method also includes forming a metal gate in the trench; and forming a source region and a drain region in the semiconductor substrate.
摘要翻译：提供了制造金属栅极晶体管的方法。该方法包括：提供半导体衬底; 以及在所述半导体衬底上形成电介质层。该方法还包括在电介质层上形成至少一个虚拟栅极; 以及在所述伪栅极周围形成第一侧壁间隔物。此外，该方法包括：通过使用第一侧壁间隔件和伪栅极作为蚀刻掩模蚀刻介电层，形成具有从伪栅极的侧壁突出并垂直于半导体衬底的侧壁的栅极电介质层; 并且去除伪栅极以形成沟槽。此外，该方法还包括在沟槽中形成金属栅极; 以及在所述半导体衬底中形成源区和漏区。

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