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61. 发明申请

US20170192908A1 DEVICE AND METHOD FOR STORING DATA IN A PLURALITY OF MULTI-LEVEL CELL MEMORY CHIPS 有权
公开(公告)号：US20170192908A1
公开(公告)日：2017-07-06
申请号：US15467348
申请日：2017-03-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Tobias Blaettler , Thomas Mittelholzer , Nikolaos Papandreou , Thomas Parnell , Charalampos Pozidis , Milos Stanisavljevic
IPC分类号： G06F12/14 , G06F11/10 , G11C11/56 , G11C7/10 , G06F21/60 , H04L9/06
CPC分类号： G06F11/1048 , G06F11/1072 , G11C7/1006 , G11C11/56 , G11C11/5628 , G11C16/10 , G11C2211/5648
摘要： A device for storing data in a plurality of multi-level cell memory chips. The device includes a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of candidate scrambled sequences of data, the result of each cost function being indicative of a balancing degree of subsequences of a candidate scrambled sequence, when the subsequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips, a selection unit to select one of the candidate scrambled sequences of data based on the results of the cost functions, and a storing unit to store the selected candidate scrambled sequence of data in the multi-level cell memory chips by storing the subsequences across the multi-level memory chips.

62. 发明授权

US09672910B2 Memory architecture for storing data in a plurality of memory chips 有权
公开(公告)号：US09672910B2
公开(公告)日：2017-06-06
申请号：US14248377
申请日：2014-04-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Theodore Antonakopoulos , Nikolaos Papandreou , Charalampos Pozidis
IPC分类号： G06F12/00 , G11C14/00 , G11C7/10 , G11C11/56 , G11C13/00 , G11C5/06
CPC分类号： G11C14/009 , G11C5/066 , G11C7/10 , G11C7/1003 , G11C7/1006 , G11C11/5678 , G11C13/0004
摘要： A memory system for storing data in a plurality N of memory chips. The memory system includes a number K of sets of memory chips, wherein each set of the K sets includes a number M of the memory chips, with N=K·M; and one signal processing unit having a number L of signal processing engines for signal processing data of the N memory chips and having a data link interface for interfacing each of the K sets.

63. 发明授权

US09647694B2 Diagonal anti-diagonal memory structure 有权
公开(公告)号：US09647694B2
公开(公告)日：2017-05-09
申请号：US14583738
申请日：2014-12-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Tobias Blaettler , Charles J. Camp , Thomas Mittelholzer , Nikolaos Papandreou , Thomas Parnell , Charalampos Pozidis
IPC分类号： G06F3/06 , H03M13/29
CPC分类号： H03M13/2921 , G06F3/0613 , G06F3/0619 , G06F3/0644 , G06F3/0673 , H03M13/616
摘要： A quarter product code codeword includes various R code symbols and C code symbols each including a plurality of symbols. Each symbol is loaded into a diagonal anti-diagonal structure in two unique locations. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol is positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.

64. 发明申请

US20170125095A1 ESTIMATION OF LEVEL-THRESHOLDS FOR MEMORY CELLS 审中-公开
公开(公告)号：US20170125095A1
公开(公告)日：2017-05-04
申请号：US15404314
申请日：2017-01-12
申请人： International Business Machines Corporation
发明人： Thomas Mittelholzer , Nikolaos Papandreou , Thomas Parnell , Charalampos Pozidis , Milos Stanisavljevic
IPC分类号： G11C13/00 , G11C11/56
CPC分类号： G11C13/004 , G11C7/1006 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0054
摘要： Methods and apparatus are provided for determining level-thresholds for q-level memory cells. A group of the memory cells are read to obtain respective read signal components. The read signal components are processed in dependence on signal level to produce a signal level vector, comprising a series of elements, indicative of the distribution of read signal components in order of signal level. A plurality of possible sets of q−1 elements corresponding, respectively, to q−1 level-thresholds which partition the signal level vector into q segments, is then defined. The q−1 level-thresholds for the group of memory cells are then determined by selecting from said possible sets that set for which a predetermined difference function, dependent on differences in signal level for elements in each of said q segments for the set, has an optimum value.

65. 发明申请

US20170123660A1 BACKGROUND THRESHOLD VOLTAGE SHIFTING USING BASE AND DELTA THRESHOLD VOLTAGE SHIFT VALUES IN NON-VOLATILE MEMORY 有权
公开(公告)号：US20170123660A1
公开(公告)日：2017-05-04
申请号：US15405162
申请日：2017-01-12
申请人： International Business Machines Corporation
发明人： Charles J. Camp , Timothy J. Fisher , Aaron D. Fry , Nikolas Ioannou , Ioannis Koltsidas , Nikolaos Papandreou , Thomas Parnell , Roman Pletka , Charalampos Pozidis , Sasa Tomic
IPC分类号： G06F3/06 , G11C16/14
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C29/021 , G11C29/028 , G11C2029/0409
摘要： In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVSΔ) values configured to track temporary changes with respect to changes in the underlying threshold voltage distributions due to retention and/or read disturb errors. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block, the one or more overall threshold voltage shift values being a function of the one or more TVSΔ values to be used when writing data to the non-volatile memory block. The one or more overall threshold voltage shift values are stored.

66. 发明授权

US09496043B1 Dynamically optimizing flash data retention or endurance based on data write frequency 有权
标题翻译：基于数据写入频率动态优化闪存数据保留或持久性
公开(公告)号：US09496043B1
公开(公告)日：2016-11-15
申请号：US14749206
申请日：2015-06-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Charles J. Camp , Timothy J. Fisher , Aaron D. Fry , Nikolaos Papandreou , Thomas Parnell , Charalampos Pozidis , Andrew D. Walls
IPC分类号： G11C16/04 , G11C16/14 , G11C16/34 , G11C16/16 , G11C16/26
CPC分类号： G11C16/26 , G06F2212/1036 , G11C16/16 , G11C16/3459 , G11C16/349
摘要： In a data storage system including a non-volatile memory array, a controller determines a write frequency of a logical address mapped to a physical subset of the non-volatile memory array. Based on the determined write frequency of the logical address, the controller dynamically adjusts at least one operating parameter of a program/erase (P/E) cycle to optimize at least one of endurance of the block and data retention time of the physical subset of the non-volatile memory array. The at least one operating parameter includes one or more of a set including a pulse budget, a verify voltage and a verify threshold.
摘要翻译：在包括非易失性存储器阵列的数据存储系统中，控制器确定映射到非易失性存储器阵列的物理子集的逻辑地址的写入频率。基于所确定的逻辑地址的写入频率，控制器动态地调整程序/擦除（P / E）周期的至少一个操作参数，以优化块的持久性和物理子集的数据保留时间中的至少一个非易失性存储器阵列。所述至少一个操作参数包括包括脉冲预算，验证电压和验证阈值的集合中的一个或多个。

67. 发明授权

US09305639B2 Read-detection in multi-level cell memory 有权
标题翻译：多级单元存储器中的读取检测
公开(公告)号：US09305639B2
公开(公告)日：2016-04-05
申请号：US14251734
申请日：2014-04-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas Mittelholzer , Nikolaos Papandreou , Charalampos Pozidis
IPC分类号： G11C29/56 , G11C11/56 , G11C13/00
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0679 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2211/5648
摘要： A method and apparatus for detecting N-symbol codewords. The method including: reading q-level memory cells to obtain a read signal having N signal components; detecting the memory cell level corresponding to each component using a first correspondence criterion dependent on reference signal levels; identifying unreliable components; detecting, for each unreliable component, the next-most-closely corresponding memory cell level according to the first correspondence criterion; defining a set of ordered codeword vectors having N symbols corresponding to respective components of the read signal ordered according to a signal level, wherein the symbol values in each ordered codeword vector correspond to one combination of detected memory cell levels; defining, for each read signal, candidate initial vectors having intersected the ordered codeword vectors and plurality of initial vectors; and detecting, if the candidate initial vectors contains a vector, the codeword corresponding to that read signal that depends on the candidate initial vectors.
摘要翻译：一种用于检测N个符号码字的方法和装置。该方法包括：读取q级存储单元以获得具有N个信号分量的读信号; 使用取决于参考信号电平的第一对应标准来检测对应于每个分量的存储器单元级; 识别不可靠的组件; 根据第一对应标准，针对每个不可靠分量检测最接近相应的存储单元级; 定义具有对应于根据信号电平排序的读取信号的各个分量的N个符号的一组有序码字矢量，其中每个有序码字矢量中的符号值对应于检测到的存储器单元电平的一个组合; 为每个读取信号定义已经与有序码字矢量和多个初始矢量相交的候选初始矢量; 以及如果候选初始向量包含向量，则检测与取决于候选初始向量的该读取信号相对应的码字。

68. 发明授权

US09251909B1 Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory 有权
标题翻译：使用闪存中的基极和Δ阈值电压偏移值的背景阈值电压偏移
公开(公告)号：US09251909B1
公开(公告)日：2016-02-02
申请号：US14500900
申请日：2014-09-29
申请人： International Business Machines Corporation
发明人： Charles J. Camp , Timothy J. Fisher , Aaron D. Fry , Nikolas Ioannou , Ioannis Koltsidas , Nikolaos Papandreou , Thomas Parnell , Roman Pletka , Charalampos Pozidis , Sasa Tomic
IPC分类号： G11C16/10 , G11C16/34 , G11C16/14 , G11C16/26
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C29/021 , G11C29/028 , G11C2029/0409
摘要： In one embodiment, a method for managing threshold voltage shifts in Flash memory includes determining, by a processor after writing data to a Flash memory block, base threshold voltage shift (TVSBASE) value(s) configured to track permanent changes in underlying threshold voltage distributions due to cycling of the Flash memory block, determining, after the writing of data to the Flash memory block, delta threshold voltage shift (TVSΔ) value(s) configured to track temporary changes, with respect to changes in the underlying threshold voltage distributions due to retention and/or read disturb errors, calculating an overall threshold voltage shift (TVS) value for the data written to the Flash memory block, the overall TVS value being a function of the TVSBASE and TVSΔ value(s) to be used when writing data to the Flash memory block, and applying the overall TVS value to a read operation of the data stored to the Flash memory block.
摘要翻译：在一个实施例中，一种用于管理闪速存储器中的阈值电压偏移的方法包括：在将数据写入闪速存储器块之后由处理器确定基准阈值电压偏移（TVSBASE）值，其被配置为跟踪潜在阈值电压分布的永久变化由于闪速存储器块的循环，在将数据写入闪存块之后，确定配置为跟踪临时变化的阈值电压偏移（TVS＆Dgr）值相对于基础阈值电压分布的变化由于保留和/或读取干扰错误，计算写入闪存块的数据的总体阈值电压偏移（TVS）值，整体TVS值是TVSBASE和TVS＆Dgr的函数; 将数据写入闪存块时要使用的值，以及将整体TVS值应用于存储到闪存块的数据的读取操作。

69. 发明申请

US20150287456A1 DETERMINING A CELL STATE OF A RESISTIVE MEMORY CELL 有权
公开(公告)号：US20150287456A1
公开(公告)日：2015-10-08
申请号：US14742363
申请日：2015-06-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Nikolaos Papandreou , Charalampos Pozidis , Abu Sebastian , Milos Stanisavljevic
IPC分类号： G11C13/00 , G11C11/56
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0057 , G11C2213/79
摘要： A device for determining an actual cell state of a resistive memory cell having a plurality M of programmable cell states comprising a sensing circuit, a settling circuit, a prebiasing circuit, and a resistor coupled in parallel to the resistive memory cell, wherein the resistor is configured to reduce an effective resistance seen by the prebiasing circuit. The sensing circuit is configured to sense a sensing voltage of the resistive memory cell and output a resultant value in response to the sensing voltage which is indicative for the actual cell state. The settling circuit is configured to settle the sensing voltage to a certain target voltage representing one of the M programmable cell states. The prebiasing circuit is configured to prebiase a bitline capacitance of the resistive memory cell such the sensing voltage is close to the certain target voltage.

70. 发明申请

US20140325124A1 MEMORY SYSTEM AND METHOD FOR OPERATING A MEMORY SYSTEM 有权
标题翻译：用于操作存储器系统的存储器系统和方法
公开(公告)号：US20140325124A1
公开(公告)日：2014-10-30
申请号：US14248377
申请日：2014-04-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Theodore Antonakopoulos , Nikolaos Papandreou , Charalampos Pozidis
IPC分类号： G06F3/06 , G11C14/00
CPC分类号： G11C14/009 , G11C5/066 , G11C7/10 , G11C7/1003 , G11C7/1006 , G11C11/5678 , G11C13/0004
摘要： A memory system for storing data in a plurality N of memory chips. The memory system includes a number K of sets of memory chips, wherein each set of the K sets includes a number M of the memory chips, with N=K·M; and one signal processing unit having a number L of signal processing engines for signal processing data of the N memory chips and having a data link interface for interfacing each of the K sets.
摘要翻译：一种用于将数据存储在多个存储器芯片中的存储器系统。存储器系统包括K组的存储器芯片，其中K组的每组包括存储器芯片的数量M，其中N = K·M; 以及一个信号处理单元，具有数目为L的用于N个存储器芯片的信号处理数据的信号处理引擎，并且具有数据链接接口用于与每个K组进行对接。

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