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61. 发明申请

US20160225634A1 METHOD FOR QUADRUPLE FREQUENCY FINFETS WITH SINGLE-FIN REMOVAL 有权
标题翻译：具有单金属去除功能的四元频率FinFET方法
公开(公告)号：US20160225634A1
公开(公告)日：2016-08-04
申请号：US14613416
申请日：2015-02-04
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/308 , H01L29/66 , H01L21/311 , H01L21/027 , H01L21/306 , H01L21/8234
CPC分类号： H01L21/3086 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L27/1211
摘要： A method of single-fin removal for quadruple density fins. A first double density pattern of first sidewall spacers is produced on a semiconductor substrate from first mandrels formed by a first mask using a minimum pitch. A second double density pattern of second sidewall spacers is produced on a layer disposed above the first double density pattern from second mandrels formed by a second mask with a the minimum pitch that is shifted relative to the first mask. A single sidewall spacer is removed from either the first or second double density pattern of first and second sidewall spacers. Sidewall image transfer processes allow the formation of quadruple density fins from which but a single fin is removed.
摘要翻译：用于四重密度翅片的单翅片去除的方法。第一侧壁间隔物的第一双重密度图案在半导体衬底上由使用最小间距的第一掩模形成的第一心轴产生。在由第二掩模形成的第二芯轴上设置有第二双重密度图案上方的第二侧壁间隔物的第二双重密度图案具有相对于第一掩模移动的最小间距。从第一和第二侧壁间隔物的第一或第二双重密度图案中去除单个侧壁间隔物。侧壁图像转印过程允许形成四重密度翅片，但是除去单个翅片。

62. 发明授权

US09373678B2 Non-planar capacitors with finely tuned capacitance values and methods of forming the non-planar capacitors 有权
标题翻译：具有微调电容值的非平面电容器和形成非平面电容器的方法
公开(公告)号：US09373678B2
公开(公告)日：2016-06-21
申请号：US14306294
申请日：2014-06-17
申请人： International Business Machines Corporation
发明人： Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/20 , H01L27/06 , H01L49/02 , H01L29/78 , H01L29/66 , H01L21/308 , H01L21/84 , H01L27/12
CPC分类号： H01L28/40 , H01L21/3086 , H01L21/845 , H01L27/0629 , H01L27/1207 , H01L28/60 , H01L28/91 , H01L29/66795 , H01L29/785
摘要： Disclosed are non-planar capacitors with finely tuned capacitances and methods of forming them. The capacitors each incorporate one or more semiconductor bodies and one or more gate stacks traversing the one or more semiconductor bodies. At least one first semiconductor body is etched so that it is shorter in length than the others, which are incorporated into other non-planar devices and/or into the same non-planar capacitor. Additionally, at least one gate stack can be formed so that it traverses a first portion and, particularly, an end portion of the shortened semiconductor body and further so that it extends laterally some distance beyond that first portion. In such capacitors, the length of the first portion of the shorted semiconductor body, which corresponds to a capacitor conductor and which is traversed by the gate stack, which corresponds to a capacitor dielectric and another capacitor conductor, is predetermined to achieve a desired capacitance.
摘要翻译：公开了具有微调电容的非平面电容器及其形成方法。电容器各自包括一个或多个半导体本体和穿过一个或多个半导体主体的一个或多个栅极叠层。蚀刻至少一个第一半导体本体，使得其长度比其它半导体本体短，其被并入其它非平面器件和/或并入相同的非平面电容器中。此外，可以形成至少一个栅极堆叠，使得其穿过第一部分，特别是穿过缩短的半导体本体的端部，并且进一步使其横向延伸超过该第一部分一段距离。在这种电容器中，对应于电容器导体的电容器导体的对应于电容器电介质和另一个电容器导体的电容器导体的短路半导体本体的第一部分的长度被预先确定以获得所需的电容。

63. 发明申请

US20160133730A1 JUNCTIONLESS TUNNEL FET WITH METAL-INSULATOR TRANSITION MATERIAL 有权
公开(公告)号：US20160133730A1
公开(公告)日：2016-05-12
申请号：US14876006
申请日：2015-10-06
申请人： International Business Machines Corporation
发明人： Mohit Bajaj , Suresh Gundapaneni , Aniruddha Konar , Kota V.R.M. Murali , Edward J. Nowak
IPC分类号： H01L29/66 , H01L29/10 , H01L29/51 , H01L29/78
CPC分类号： H01L29/66977 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/1033 , H01L29/42364 , H01L29/42372 , H01L29/4908 , H01L29/511 , H01L29/517 , H01L29/66795 , H01L29/7855 , H01L29/78645 , H01L29/78648 , H01L49/003
摘要： Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.

64. 发明申请

US20160118496A1 SEMICONDUCTOR STRUCTURES WITH FIELD EFFECT TRANSISTOR(S) HAVING LOW-RESISTANCE SOURCE/DRAIN CONTACT(S) 有权
标题翻译：具有低电阻源/漏极触点的场效应晶体管的半导体结构（S）
公开(公告)号：US20160118496A1
公开(公告)日：2016-04-28
申请号：US14523083
申请日：2014-10-24
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Jeffrey B. Johnson , Edward J. Nowak
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L23/5283 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L29/0847 , H01L29/41775 , H01L29/66484 , H01L29/66545 , H01L29/66795 , H01L29/7831 , H01L29/7851
摘要： Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods.
摘要翻译：公开了包括具有低电阻源极/漏极接触和可选地低栅极 - 源极/漏极接触电容的场效应晶体管（FET）的半导体结构。该结构包括半导体本体，并包含在其中，第一和第二源极/漏极区域和沟道区域。第一栅极在沟道区域处与半导体本体相邻，并且第二非功能栅极与半导体本体相邻，使得第二源极/漏极区域位于第一和第二栅极之间。第一和第二源极/漏极触点分别位于第一和源极/漏极区域上。第二源极/漏极触点比第一源极/漏极触点更宽，因此具有较低的电阻。此外，第一和第二源极/漏极接触件相对于第一栅极的间隔可以使得第一栅极至第二源极/漏极接触电容等于或小于第一栅极至第一源极/漏极接触电容。还公开了相关的形成方法。

65. 发明申请

US20160056181A1 METHODS OF FORMING FIELD EFFECT TRANSISTORS USING A GATE CUT PROCESS FOLLOWING FINAL GATE FORMATION 有权
标题翻译：使用栅极切割过程形成场效应晶体管的方法
公开(公告)号：US20160056181A1
公开(公告)日：2016-02-25
申请号：US14462631
申请日：2014-08-19
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L27/12 , H01L21/762 , H01L21/8234 , H01L29/66 , H01L29/49 , H01L29/51 , H01L27/088 , H01L29/06 , H01L21/265 , H01L21/84 , H01L21/3105
CPC分类号： H01L21/28123 , H01L21/265 , H01L21/26513 , H01L21/31053 , H01L21/762 , H01L21/76283 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L21/823878 , H01L21/845 , H01L23/528 , H01L27/0886 , H01L27/0924 , H01L27/1211 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1033 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/6681
摘要： Disclosed are field effect transistor (FET) formation methods using a final gate cut process and the resulting structures. One method forms an elongated gate across first and second semiconductor bodies for first and second FETs, respectively. An opening is formed in a portion of the elongated gate between the semiconductor bodies, cutting at least the gate conductor layer. The opening is filled with an isolation layer, thereby forming an isolation region that segments the elongated gate into first and second gates for the first and second FETs, respectively. Another method forms at least three gates across an elongated semiconductor body. An isolation region is formed that extends, not only through a portion of a center one of the gates, but also through a corresponding portion of the elongated semiconductor body adjacent to that gate, thereby segmenting the elongated semiconductor body into discrete semiconductor bodies for first and second FETs.
摘要翻译：公开了使用最终栅极切割工艺和所得结构的场效应晶体管（FET）形成方法。一种方法分别在第一和第二半导体本体上形成用于第一和第二FET的细长栅极。在半导体体之间的细长栅极的一部分上形成开口，至少切割栅极导体层。开口填充有隔离层，从而形成隔离区域，其将细长栅极分别分成用于第一和第二FET的第一和第二栅极。另一种方法形成跨越细长半导体体的至少三个栅极。形成隔离区，其不仅通过栅极的中心一部分的一部分延伸，而且延伸穿过与该栅极相邻的细长半导体本体的对应部分，从而将细长半导体本体分成第一和第第二个FET。

66. 发明申请

US20150333156A1 DIELECTRIC FILLER FINS FOR PLANAR TOPOGRAPHY IN GATE LEVEL 审中-公开
公开(公告)号：US20150333156A1
公开(公告)日：2015-11-19
申请号：US14808914
申请日：2015-07-24
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Ramachandra Divakaruni , Bruce B. Doris , Ali Khakifirooz , Edward J. Nowak , Kern Rim
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06
CPC分类号： H01L29/66795 , H01L21/845 , H01L27/1211 , H01L29/0653 , H01L29/785
摘要： An array of stacks containing a semiconductor fins and an oxygen-impermeable cap is formed on a semiconductor substrate with a substantially uniform areal density. Oxygen-impermeable spacers are formed around each stack, and the semiconductor substrate is etched to vertically extend trenches. Semiconductor sidewalls are physically exposed from underneath the oxygen-impermeable spacers. The oxygen-impermeable spacers are removed in regions in which semiconductor fins are not needed. A dielectric oxide material is deposited to fill the trenches. Oxidation is performed to convert a top portion of the semiconductor substrate and semiconductor fins not protected by oxygen-impermeable spacers into dielectric material portions. Upon removal of the oxygen-impermeable caps and remaining oxygen-impermeable spacers, an array including semiconductor fins and dielectric fins is provided. The dielectric fins alleviate variations in the local density of protruding structures, thereby reducing topographical variations in the height of gate level structures to be subsequently formed.

67. 发明授权

US09170165B2 Workfunction modulation-based sensor to measure pressure and temperature 有权
标题翻译：基于功能调制的传感器来测量压力和温度
公开(公告)号：US09170165B2
公开(公告)日：2015-10-27
申请号：US13849565
申请日：2013-03-25
申请人： International Business Machines Corporation
发明人： Balaji Jayaraman , Kota V. R. M. Murali , Edward J. Nowak , Ninad D. Sathaye , Rajesh Sathiyanarayanan
IPC分类号： G01N7/00 , G01L9/00 , G01K7/01 , G01N27/414 , G01N27/00
CPC分类号： G01L9/0042 , G01K7/015 , G01N27/002 , G01N27/4141
摘要： A workfunction modulation-based sensor comprising a field-effect transistor (FET). The FET comprises a substrate, a gate dielectric, a metal gate, a source, a drain, and a layer of sensing material that is electrically connected to the metal gate. An electrical connection that connects to the source of the FET. An electrical connection that connects to the drain of the FET. An electrical connection that connects to the layer of sensing material. An environment that includes an adsorbate gas surrounding, at least a portion of, the layer of sensing material. Wherein the sensing material is adapted to adsorb, at least in part, the adsorbate gas. The amount of adsorbate gas adsorbed on the layer of sensing material modulates the workfunction of the FET such that the degree of adsorbate gas adsorption corresponds to one of the temperature or pressure associated with the environment of the FET.
摘要翻译：一种基于功能调制的传感器，包括场效应晶体管（FET）。 FET包括电连接到金属栅极的衬底，栅极电介质，金属栅极，源极，漏极和感测材料层。连接到FET源极的电气连接。连接到FET的漏极的电气连接。连接到传感材料层的电气连接。环境，其包括围绕传感材料层的至少一部分的被吸附气体。其中感测材料适于至少部分吸附被吸附物质气体。吸附在感应材料层上的吸附气体的量调节FET的功函数，使得吸附气体吸附的程度对应于与FET的环境相关的一个温度或压力。

68. 发明授权

US09105707B2 ZRAM heterochannel memory 有权
标题翻译： ZRAM异或通道存储器
公开(公告)号：US09105707B2
公开(公告)日：2015-08-11
申请号：US13949609
申请日：2013-07-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Andres Bryant , Lyndon R. Logan , Edward J. Nowak , Robert R. Robison
IPC分类号： H01L29/78 , H01L29/66 , H01L27/12 , H01L27/108
CPC分类号： H01L29/78 , H01L27/10802 , H01L27/1203 , H01L29/66666 , H01L29/7841
摘要： Approaches for zero capacitance memory cells are provided. A method of manufacturing a semiconductor structure includes forming a channel region by doping a first material with a first type of impurity. The method includes forming source/drain regions by doping a second material with a second type of impurity different than the first type of impurity, wherein the second material has a smaller bandgap than the first material. The method includes forming lightly doped regions between the channel region and the source/drain regions, wherein the lightly doped regions include the second material. The method includes forming a gate over the channel region, wherein the second material extends under edges of the gate.
摘要翻译：提供零电容存储单元的方法。制造半导体结构的方法包括通过掺杂第一种杂质的第一材料形成沟道区。该方法包括通过用不同于第一种类型杂质的第二类型杂质掺杂第二材料来形成源极/漏极区域，其中第二材料具有比第一材料更小的带隙。该方法包括在沟道区域和源极/漏极区域之间形成轻掺杂区域，其中轻掺杂区域包括第二材料。该方法包括在通道区域上形成栅极，其中第二材料在栅极的边缘延伸。

69. 发明申请

US20150221767A1 SEMICONDUCTOR STRUCTURES WITH PAIR(S) OF VERTICAL FIELD EFFECT TRANSISTORS, EACH PAIR HAVING A SHARED SOURCE/DRAIN REGION AND METHODS OF FORMING THE STRUCTURES 有权
标题翻译：垂直场效应晶体管，具有共享源/漏区的每个对象的半导体结构和形成结构的方法
公开(公告)号：US20150221767A1
公开(公告)日：2015-08-06
申请号：US14169318
申请日：2014-01-31
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/66666 , H01L21/3086 , H01L21/823425 , H01L21/823487 , H01L21/84 , H01L27/1203 , H01L29/42392 , H01L29/66484 , H01L29/7827 , H01L29/7831
摘要： Disclosed are semiconductor structures and methods of forming the structures. The structures each comprise a pair of vertical FETs. Specifically, a U-shaped semiconductor body has a horizontal section and two vertical sections. The horizontal section comprises a shared source/drain region for first and second vertical FETs. Each vertical section comprises a channel region and a source/drain region above the channel region for a corresponding one the vertical FETs. In one semiconductor structure, each vertical section has a gate wrapped around the channel region. In another semiconductor structure, each vertical section has a front gate positioned adjacent to the inner vertical surface at the channel region and a back gate positioned adjacent to the outer vertical surface at the channel region. In any case, a contact, which is electrically isolated from the gates, extends vertically to the shared source/drain region in the horizontal section. Optionally, metal strap(s) electrically connect the pair of vertical FETs to adjacent pair(s).
摘要翻译：公开了形成结构的半导体结构和方法。这些结构各自包括一对垂直FET。具体地说，U形半导体本体具有水平截面和两个垂直截面。水平部分包括用于第一和第二垂直FET的共享源极/漏极区域。每个垂直部分包括沟道区域和沟道区域上方的源极/漏极区域，用于相应的一个垂直FET。在一个半导体结构中，每个垂直部分具有缠绕在沟道区域周围的栅极。在另一个半导体结构中，每个垂直部分具有位于相邻于通道区域处的内部垂直表面的前门和位于沟道区域处与外部垂直表面相邻的后门。在任何情况下，与栅极电隔离的触点在水平部分中垂直延伸到共享的源极/漏极区域。可选地，金属带将一对垂直FET电连接到相邻对。

70. 发明授权

US09041107B2 Devices with gate-to-gate isolation structures and methods of manufacture 有权
标题翻译：具有栅极到栅极隔离结构的器件和制造方法
公开(公告)号：US09041107B2
公开(公告)日：2015-05-26
申请号：US13833735
申请日：2013-03-15
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/12 , H01L29/06 , H01L21/02 , H01L21/762 , H01L21/84
CPC分类号： H01L29/0649 , H01L21/02038 , H01L21/76283 , H01L21/845
摘要： Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad films and a portion of the underlying substrate, each of which are separated by a trench. The method further includes removing portions of the second plurality of fins resulting in a height lower than a height of the plurality of fins including the isolation structures. The method further includes forming gate electrodes within each trench, burying the second plurality of fins and abutting sides of the plurality of fins including the isolation structures. The plurality of fins including the isolation structures electrically and physically isolate adjacent gate electrode of the gate electrodes.
摘要翻译：提供具有栅极到栅极隔离结构和制造方法的器件。该方法包括在衬垫膜和下面的衬底中形成多个隔离结构。该方法还包括形成包括隔离结构的多个翅片和包括两个垫片膜的第二多个翅片以及下面的衬底的一部分，每个鳍片由沟槽分开。该方法还包括去除第二多个翅片的部分，导致比包括隔离结构的多个翅片的高度低的高度。该方法还包括在每个沟槽内形成栅电极，将第二多个鳍片和包括隔离结构的多个翅片的邻接侧面相互掩埋。包括隔离结构的多个翅片电和物理地隔离栅电极的相邻栅电极。

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