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61. 发明授权

US09721848B1 Cutting fins and gates in CMOS devices 有权
公开(公告)号：US09721848B1
公开(公告)日：2017-08-01
申请号：US15337189
申请日：2016-10-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Huiming Bu , Kangguo Cheng , Andrew M. Greene , Dechao Guo , Sivananda K. Kanakasabapathy , Gauri Karve , Balasubramanian S. Pranatharthiharan , Stuart A. Sieg , John R. Sporre , Gen Tsutsui , Rajasekhar Venigalla , Huimei Zhou
IPC分类号： H01L21/8238 , H01L29/66 , H01L27/092 , H01L29/08 , H01L29/06 , H01L29/78
CPC分类号： H01L21/823878 , H01L21/823431 , H01L21/823481 , H01L21/823814 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L29/0653 , H01L29/0847 , H01L29/66545 , H01L29/7848
摘要： A semiconductor device includes a first fin and a second fin arranged on a substrate, a gate stack arranged over a channel region of the first fin, and spacers arranged along sidewalls of the gate stack. A cavity is arranged adjacent to a distal end of the gate stack. The cavity is defined by the substrate, a distal end of the second fin, and the spacers. A dielectric fill material is arranged in the cavity such that the dielectric fill material contacts the substrate, the distal end of the second fin, and the spacers.

62. 发明申请

US20170170171A1 METHOD OF CUTTING FINS TO CREATE DIFFUSION BREAKS FOR FINFETS 有权
公开(公告)号：US20170170171A1
公开(公告)日：2017-06-15
申请号：US14964445
申请日：2015-12-09
申请人： International Business Machines Corporation
发明人： Hemanth Jagannathan , Sivananda K. Kanakasabapathy , Alexander Reznicek
IPC分类号： H01L27/088 , H01L21/311 , H01L21/02 , H01L29/66
CPC分类号： H01L27/0886 , H01L21/02532 , H01L21/31122 , H01L21/31144 , H01L21/823431 , H01L21/823481 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785
摘要： A method is provided for forming an integrated circuit with FinFETs. Initially, a fin is received with a dummy gate passing thereover. The dummy gate is removed to form a space over the fin. A temporary layer is subsequently placed in the space, and an element from the temporary layer is caused to pass into a portion of the fin to form a modified fin portion. After the temporary layer is removed, at least part of the modified fin portion is etched away to form a gap in the fin.

63. 发明申请

US20170162685A1 STRESS RETENTION IN FINS OF FIN FIELD-EFFECT TRANSISTORS 有权
公开(公告)号：US20170162685A1
公开(公告)日：2017-06-08
申请号：US14956711
申请日：2015-12-02
申请人： International Business Machines Corporation
发明人： Sivananda K. Kanakasabapathy , Gauri Karve , Juntao Li , Fee Li Lie , Stuart A. Sieg , John R. Sporre
IPC分类号： H01L29/78 , H01L29/66 , H01L21/308 , H01L29/06
CPC分类号： H01L29/6681 , H01L21/3086 , H01L21/823431 , H01L21/845 , H01L27/1211 , H01L29/0649 , H01L29/42356 , H01L29/66795 , H01L29/7842 , H01L29/7845 , H01L29/7846 , H01L29/785
摘要： Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

64. 发明授权

US09515089B1 Bulk fin formation with vertical fin sidewall profile 有权
标题翻译：具有垂直翅片侧壁轮廓的散装翅片形成
公开(公告)号：US09515089B1
公开(公告)日：2016-12-06
申请号：US14712072
申请日：2015-05-14
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Hong He , Sivananda K. Kanakasabapathy , Chiahsun Tseng , Yunpeng Yin
IPC分类号： H01L21/84 , H01L27/12 , H01L21/762 , H01L21/311 , H01L29/66 , H01L21/308 , H01L21/3065 , H01L21/02
CPC分类号： H01L27/0886 , H01L21/02236 , H01L21/02255 , H01L21/3065 , H01L21/3081 , H01L21/3086 , H01L21/31116 , H01L21/31144 , H01L21/76202 , H01L21/823431 , H01L21/845 , H01L27/1211 , H01L29/165 , H01L29/6653 , H01L29/6656
摘要： Fabricating a semiconductor device includes providing a substrate, wherein the substrate is comprised of a base layer, a doped silicon layer on top of the base layer, and an undoped silicon layer on top of the doped silicon layer; forming a hard mask layer on top of the substrate; forming at least one mandrel on top of the hard mask layer; forming a spacer layer on top of exposed portions of the hard mask layer and the at least one mandrel; etching portions of the spacer layer; removing the at least one mandrel; etching regions of the hard mask layer and the undoped silicon layer not protected by remaining portions of the spacer layer to form at least one fin; and removing the remaining portions of the spacer layer.
摘要翻译：制造半导体器件包括提供衬底，其中衬底由基底层，基底层顶部的掺杂硅层和掺杂硅层顶部的未掺杂硅层构成; 在所述基板的顶部上形成硬掩模层; 在所述硬掩模层的顶部上形成至少一个心轴; 在所述硬掩模层和所述至少一个心轴的暴露部分的顶部上形成间隔层; 蚀刻间隔层的部分; 移除所述至少一个心轴; 蚀刻所述硬掩模层和未掺杂的硅层的区域，而不被所述间隔层的剩余部分保护以形成至少一个鳍; 并去除间隔层的剩余部分。

65. 发明授权

US09472506B2 Registration mark formation during sidewall image transfer process 有权
标题翻译：侧壁图像转印过程中的注册标志形成
公开(公告)号：US09472506B2
公开(公告)日：2016-10-18
申请号：US14630715
申请日：2015-02-25
申请人： International Business Machines Corporation
发明人： David J. Conklin , Allen H. Gabor , Sivananda K. Kanakasabapathy , Byeong Y. Kim , Fee Li Lie , Stuart A. Sieg
IPC分类号： H01L21/308 , H01L23/544 , H01L21/311 , H01L21/033
CPC分类号： H01L23/544 , G03F7/70633 , G03F7/70683 , G03F9/708 , H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/3086 , H01L21/31111 , H01L21/31144 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453
摘要： Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.
摘要翻译：提供了在形成亚光刻结构期间形成诸如对准标记或重叠标记的对准标记的方法。方法可以包括在半导体层上的硬掩模上形成多个心轴，每个心轴包括与其相邻的间隔物。选择多个心轴中的至少一个心轴，并且在所述至少一个选定心轴上形成掩模。离开间隔物去除多个心轴，掩模防止去除至少一个选定的心轴。去除面具。第一蚀刻使用间隔物作为亚光刻结构的图案和至少一个选定的心轴和用于对准标记的相邻间隔物，将亚光刻结构和对准标记图案化成硬掩模。第二蚀刻使用图案化的硬掩模在半导体层中形成次光刻结构，并使用至少一个选定的心轴和图案化的硬掩模在半导体层中形成对准标记。

66. 发明申请

US20160197157A1 REPLACEMENT METAL GATE STACK FOR DIFFUSION PREVENTION 有权
公开(公告)号：US20160197157A1
公开(公告)日：2016-07-07
申请号：US15068218
申请日：2016-03-11
申请人： International Business Machines Corporation
发明人： Takashi Ando , Johnathan E. Faltermeier , Su Chen Fan , Sivananda K. Kanakasabapathy , Injo Ok , Tenko Yamashita
IPC分类号： H01L29/49 , H01L27/088 , H01L29/66 , H01L29/423
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823431 , H01L21/823456 , H01L21/845 , H01L27/088 , H01L29/401 , H01L29/42376 , H01L29/517 , H01L29/66545 , H01L29/66795
摘要： A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.

67. 发明授权

US09299705B2 Method of forming semiconductor fins and insulating fence fins on a same substrate 有权
标题翻译：在同一基板上形成半导体翅片和隔离栅栏翅片的方法
公开(公告)号：US09299705B2
公开(公告)日：2016-03-29
申请号：US14181781
申请日：2014-02-17
申请人： International Business Machines Corporation
发明人： Sivananda K. Kanakasabapathy
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0924 , H01L21/823821 , H01L27/11807 , H01L29/0653 , H01L29/6681 , H01L2027/11872
摘要： A semiconductor structure may be formed by forming a first semiconductor fin and a second inactive semiconductor fin above a substrate; depositing a masking layer above the first semiconductor fin and the second semiconductor fin; etching a trench in the masking layer exposing the second semiconductor fin while the first semiconductor fin remains covered by the masking layer; removing the second semiconductor fin to form a fin recess beneath the trench; filling the fin recess with an insulating material to form an insulating fence fin; and removing the masking layer to expose the first semiconductor fin and the insulating fence fin. A third semiconductor fin separating the first semiconductor fin from the second semiconductor fin may also be formed prior to depositing the masking layer and covered by the masking layer. The first semiconductor fin may be a pFET fin and the third semiconductor fin may be an nFET fin.
摘要翻译：可以通过在衬底上形成第一半导体鳍和第二非活性半导体鳍形成半导体结构; 在第一半导体鳍片和第二半导体鳍片之上沉积掩模层; 在所述掩模层中蚀刻暴露所述第二半导体鳍片的沟槽，同时所述第一半导体鳍片保持被所述掩蔽层覆盖; 移除所述第二半导体翅片以在所述沟槽下方形成翅片凹槽; 用绝缘材料填充翅片凹槽以形成绝缘栅栏; 以及去除所述掩模层以暴露所述第一半导体翅片和所述绝缘栅栏鳍。将第一半导体鳍片与第二半导体鳍片分开的第三半导体鳍片也可以在沉积掩模层之前形成并被掩蔽层覆盖。第一半导体鳍片可以是pFET鳍片，并且第三半导体鳍片可以是nFET鳍片。

68. 发明申请

US20150214244A1 STRUCTURE AND PROCESS TO DECOUPLE DEEP TRENCH CAPACITORS AND WELL ISOLATION 审中-公开
标题翻译：结构和工艺分解深层电容电容器和隔离层
公开(公告)号：US20150214244A1
公开(公告)日：2015-07-30
申请号：US14166155
申请日：2014-01-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Herbert L. Ho , Sivananda K. Kanakasabapathy , Rishikesh Krishnan , Kern Rim
IPC分类号： H01L27/12 , H01L27/08 , H01L21/324 , H01L21/306 , H01L21/762 , H01L49/02 , H01L27/02
CPC分类号： H01L27/1203 , H01L21/3065 , H01L21/76224 , H01L21/84 , H01L27/0629 , H01L28/90
摘要： Formation of deep trench capacitors and isolation structures are decoupled by completing the isolation structures prior to etching trenches for capacitors and forming capacitors therein or vice-versa. Such decoupling of the formation of these respective structures allows different materials to be used in the deep trench capacitors and the isolation structures such as use of low permeability or dielectric constant materials and/or low Young's modulus materials in isolation structures to provide reduced AC capacitive coupling across isolation structures and/or relief of stresses associated with use of high dielectric constant materials or metal-insulator-metal (MIM) structures in deep trench capacitors. Such decoupling also allows increased efficiency of use of reaction chambers for the deep trench capacitors and the isolation structures.
摘要翻译：深沟槽电容器和隔离结构的形成通过在蚀刻用于电容器的沟槽和在其中形成电容器之前完成隔离结构来解耦，反之亦然。这些相应结构的形成的这种解耦允许在深沟槽电容器和隔离结构中使用不同的材料，例如在隔离结构中使用低导磁率或介电常数材料和/或低杨氏模量材料来提供减小的AC电容耦合跨越隔离结构和/或释放与在深沟槽电容器中使用高介电常数材料或金属 - 绝缘体 - 金属（MIM）结构有关的应力。这种去耦还允许增加用于深沟槽电容器和隔离结构的反应室的使用效率。

69. 发明授权

US09064813B2 Trench patterning with block first sidewall image transfer 有权
标题翻译：沟槽图案化与块第一侧壁图像传输
公开(公告)号：US09064813B2
公开(公告)日：2015-06-23
申请号：US13866293
申请日：2013-04-19
申请人： International Business Machines Corporation
发明人： Sivananda K. Kanakasabapathy , Chiahsun Tseng , Yongan Xu , Yunpeng Yin
IPC分类号： H01L21/47 , H01L21/31 , H01L21/30 , H01L21/308 , H01L21/768
CPC分类号： H01L21/3083 , H01L21/0337 , H01L21/3081 , H01L21/31144 , H01L21/76801 , H01L21/76802 , H01L21/76816 , H01L23/544 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method including forming a tetra-layer hardmask above a substrate, the tetra-layer hardmask including a second hardmask layer above a first hardmask layer; removing a portion of the second hardmask layer of the tetra-layer hardmask within a pattern region of a structure comprising the substrate and the tetra-layer hardmask; forming a set of sidewall spacers above the tetra-layer hardmask to define a device pattern; and transferring a portion of the device pattern into the substrate and within the pattern region of the structure.
摘要翻译：一种包括在衬底上形成四层硬掩模的方法，所述四层硬掩模包括在第一硬掩模层上方的第二硬掩模层; 在包括所述基底和所述四层硬掩模的结构的图案区域内去除所述四层硬掩模的所述第二硬掩模层的一部分; 在所述四层硬掩模之上形成一组侧壁间隔物以限定器件图案; 以及将所述器件图案的一部分转移到所述衬底中并且在所述结构的图案区域内。

70. 发明申请

US20150135156A1 SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE 审中-公开
标题翻译：具有深度电容电容器的半导体结构及其制造方法
公开(公告)号：US20150135156A1
公开(公告)日：2015-05-14
申请号：US14601288
申请日：2015-01-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kevin K. Chan , Sivananda K. Kanakasabapathy , Babar A. Khan , Masaharu Kobayashi , Effendi Leobandung , Theodorus E. Standaert , Xinhui Wang
IPC分类号： G06F17/50
摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
摘要翻译：公开了一种集成的FinFET和深沟槽电容器结构及其制造方法。该方法包括在绝缘体上硅（SOI）衬底上形成至少一个深沟槽电容器。该方法还包括从SOI衬底同时从至少一个深沟槽电容器的材料和SOI散热片形成多晶硅鳍片。该方法还包括在多晶硅鳍片上形成绝缘体层。该方法还包括在多晶硅鳍片上的SOI散热片和绝缘体层上形成栅极结构。

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