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    • 63. 发明申请
    • Data management in flash memory using probability of charge disturbances
    • 使用电荷扰动概率的闪存中的数据管理
    • US20120166707A1
    • 2012-06-28
    • US12930013
    • 2010-12-22
    • Luiz M. Franca-NetoRichard Leo GalbraithTravis Roger Oenning
    • Luiz M. Franca-NetoRichard Leo GalbraithTravis Roger Oenning
    • G06F12/02
    • G11C29/50G06F11/1048G11C2029/5002
    • A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix should also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which changes in the measured dispersion value are provoked by executing a selected operation until a detectable change occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population.
    • 描述了使用系统对充电干扰操作的灵敏度和系统执行的充电干扰操作的历史的数据管理的闪存系统和方法。 在本发明的一个实施例中,对电荷干扰操作的灵敏度体现在干扰强度矩阵中,其中所选择的操作具有相关联的数值,该相关数值是该操作的相对强度的估计,以引起电荷干扰,导致导致 数据错误。 干扰强度矩阵还应包括指示电荷增益或损失的误差方向。 干扰强度矩阵可以由进行自检的装置确定,其中通过执行所选择的操作来激发测量的色散值的变化,直到发生可检测的变化。 在替代实施例中,通过从均匀群体测试所选择的单位来确定干扰强度矩阵。
    • 66. 发明授权
    • Data recording medium with servo pattern having pseudo-noise sequences
    • 具有伪噪声序列的伺服图案的数据记录介质
    • US07193800B2
    • 2007-03-20
    • US10840819
    • 2004-05-06
    • Jonathan Darrel CokerDavid Timothy FlynnRichard Leo Galbraith
    • Jonathan Darrel CokerDavid Timothy FlynnRichard Leo Galbraith
    • G11B5/09
    • G11B5/59633G11B5/59688
    • A data recording medium has tracks with pseudo-noise (PN) sequences with good autocorrelation properties as servo information for controlling the position of the recording head. A first set of alternating tracks uses a leading pseudo-random binary sequence (PRBS), which is a PN sequence with good autocorrelation properties, and a following PRBS that is cyclically shifted from the leading PRBS. A second set of alternating tracks interleaved with the first set also has a leading PRBS and a following PRBS that is cyclically shifted from the leading PRBS, but the leading PRBS in each of the tracks in the second set is offset along-the-track from the leading PRBS in the tracks of the first set. The head positioning control system uses the leading PRBS to generate a servo timing mark (STM), the cyclic shift to generate track identification (TID), and the following PRBS from adjacent tracks to generate the head position error signal (PES).
    • 数据记录介质具有具有良好自相关特性的伪噪声(PN)序列的轨迹,作为用于控制记录头位置的伺服信息。 第一组交替轨道使用前导伪随机二进制序列(PRBS),其是具有良好自相关特性的PN序列,以及从前导PRBS循环移位的以下PRBS。 与第一组交织的第二组交替轨迹还具有前导PRBS和从前导PRBS循环移位的后续PRBS,但是第二组中的每个轨道中的前导PRBS沿着轨迹偏移 领先的PRBS在第一集的轨道。 头部定位控制系统使用前导PRBS来产生伺服定时标记(STM),循环移位以产生轨迹识别(TID),以及来自相邻轨道的后续PRBS以产生头部位置误差信号(PES)。
    • 67. 发明授权
    • Method and apparatus for enhanced timing loop for a PRML data channel
    • PRML数据通道增强定时循环的方法和装置
    • US06879629B2
    • 2005-04-12
    • US09804094
    • 2001-03-12
    • Richard Leo GalbraithDavid James Stanek
    • Richard Leo GalbraithDavid James Stanek
    • G11B20/10H03H7/40
    • G11B20/10055G11B20/10009
    • Methods and apparatus for enhanced timing loop are provided for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). An acquisition timing circuit for generating an acquisition timing signal includes a plurality of compare functions for receiving and comparing consecutive input signal samples on an interleave with a threshold value. The acquisition timing circuit includes a majority rule voting function coupled to the plurality of compare functions for selecting a timing interleave. Tracking timing circuitry for generating a timing error signal during a read operation includes a channel data detector. The channel data detector receives disk signal input samples and includes a multiple-state path memory. The tracking timing circuit includes a low latency detector receiving disk signal input samples. A selector function is coupled to an output of the low latency detector and is coupled to the multiple-state path memory for selecting a state. The selector function utilizes the low latency detector output and selects the state of the path memory. The selector function provides a low latency output corresponding to the selected state. The low latency output is used for generating the timing error signal during a read operation.
    • 为直接访问存储设备(DASD)中的部分响应最大似然(PRML)数据信道提供用于增强定时循环的方法和装置。 用于产生获取定时信号的获取定时电路包括用于接收和比较交织上的连续输入信号样本与阈值的多个比较功能。 获取定时电路包括耦合到多个比较功能的多数规则投票功能,用于选择定时交织。 用于在读取操作期间产生定时误差信号的跟踪定时电路包括通道数据检测器。 信道数据检测器接收盘信号输入样本并包括多状态路径存储器。 跟踪定时电路包括接收盘信号输入样本的低延迟检测器。 选择器功能耦合到低延迟检测器的输出,并且耦合到多状态路径存储器以选择状态。 选择器功能使用低延迟检测器输出并选择路径存储器的状态。 选择器功能提供对应于所选状态的低延迟输出。 低延迟输出用于在读取操作期间产生定时误差信号。
    • 68. 发明授权
    • Method and apparatus for thermal asperity recovery for word sync detection in data channels
    • 用于数据通道中字同步检测的热粗糙度恢复的方法和装置
    • US06583941B1
    • 2003-06-24
    • US09522111
    • 2000-03-09
    • Jonathan Darrel CokerRichard Leo GalbraithTodd Carter TruaxDonald Earl Vosberg
    • Jonathan Darrel CokerRichard Leo GalbraithTodd Carter TruaxDonald Earl Vosberg
    • G11B509
    • G11B20/24G11B5/09G11B20/1403G11B27/3027G11B27/36G11B2220/20
    • A method and apparatus are provided for thermal asperity recovery for word sync detection in data channels. A word sync field contains a plurality of word sync patterns. A word sync detector receives a read signal of the word sync field. The word sync detector identifies a first subset of the plurality of word sync patterns and starts a customer data read. When the word sync detector fails to identify the first subset of the plurality of word sync patterns, the read signal of the word sync field is received again. Then the word sync detector identifies a second predefined subset of the plurality of word sync patterns and starts a customer data read. A single word sync field is used instead of the conventional dual word sync fields required for each sector. The second predefined subset of the plurality of word sync patterns is smaller than the first subset. For example, when the first subset is defined as 4 of 8, the second predefined subset is 2 of 8. For example, when the first subset is defined as 6 of 12, the second predefined subset is 2 of 12.
    • 提供了一种用于数据通道中的词同步检测的热凹凸恢复的方法和装置。 字同步字段包含多个字同步模式。 字同步检测器接收字同步字段的读信号。 字同步检测器识别多个字同步模式的第一子集,并开始客户数据读取。 当字同步检测器不能识别多个字同步模式的第一子集时,再次接收字同步字段的读信号。 然后,字同步检测器识别多个字同步模式的第二预定义子集,并开始客户数据读取。 使用单个字同步字段而不是每个扇区所需的常规双字同步字段。 多个字同步模式的第二预定义子集小于第一子集。 例如,当第一子集被定义为8的4时,第二预定义子集是8的第二子集。例如,当第一子集被定义为12的第6子集时,第二预定义子集是12。
    • 69. 发明授权
    • Noise predictive maximum likelihood (NPML) detection methods and
apparatus based thereon
    • 基于此的噪声预测最大似然(NPML)检测方法和装置
    • US06104766A
    • 2000-08-15
    • US715174
    • 1996-09-17
    • Jonathan Darrel CokerEvangelos Stavros EleftheriouRichard Leo GalbraithWalter Hirt
    • Jonathan Darrel CokerEvangelos Stavros EleftheriouRichard Leo GalbraithWalter Hirt
    • G11B20/18G11B20/10H03M13/23H04L25/08H04L25/497H03D1/00
    • G11B20/10175G11B20/10009G11B20/10055H04L25/497
    • The invention is family of noise predictive maximum liklihood (NPML) symbol detectors that are particularly useful in direct access storage devices. Various embodiments representative of the family of detectors are described. In general, the NPML detectors include a sequence detector with imbedded feedback which may be preceded by a filter, e.g., a prediction error filter. The sequence of detectors, which may be Viterbi detectors, have an imbedded filter whose coefficients are determined by the convolution of the partial response (PR) or generalized PR function with the predictor coefficients and do not require multiplications and, thus, allows a simple RAM look-up for intersymbol-interference ISI cancelation. In one class of embodiments, the NPML detector comprises a prediction error filter of length N, cascaded with a sequence detector having 2.sup.K states, and a feedback filter imbedded in the sequence detector, having a length N+P-K, where P is length of the generalized PR shaping polynomial (P=2 yields PR4), and 0.ltoreq.K.ltoreq.N+P.
    • 本发明是在直接存取存储设备中特别有用的噪声预测最大似然(NPML)符号检测器系列。 描述了代表检测器系列的各种实施例。 通常,NPML检测器包括具有嵌入反馈的序列检测器,其可以在滤波器之前,例如预测误差滤波器。 可以是维特比检测器的检测器序列具有嵌入式滤波器,其系数由部分响应(PR)或广义PR函数与预测器系数的卷积确定,并且不需要乘法,并且因此允许简单的RAM 查询符号间干扰ISI取消。 在一类实施例中,NPML检测器包括长度为N的预测误差滤波器,与具有2K状态的序列检测器级联,以及嵌入在序列检测器中的反馈滤波器,其长度为N + PK,其中P为 广义PR整形多项式(P = 2产生PR4),0