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    • 61. 发明申请
    • LIGHT EMISSION CONTROL DEVICE AND LIGHT EMISSION CONTROL METHOD
    • 光发射控制装置和光发射控制方法
    • US20120288263A1
    • 2012-11-15
    • US13468741
    • 2012-05-10
    • Daisuke Yoshida
    • Daisuke Yoshida
    • G03B15/02H05B37/02
    • G03B15/05G03B7/08G03B7/16G03B2215/0514G03B2215/0525G03B2215/0592
    • A control device is provided for controlling a light emission device. The control device includes a light metering unit configured to acquire respective light metering values from a plurality of light metering regions. The control device further includes a correction unit configured to correct information about a light metering value of a target region based on a result of comparison between the light metering value of the target region and the light metering value of the light metering region at the periphery of the target region among the plurality of light metering regions, the result being acquired by the light metering unit allowing the light emission device to perform pre-flashing. Also, a calculation unit is provided which is configured to calculate a main light emission amount of the light emission device based on the information about the light metering value corrected by the correction unit.
    • 提供一种用于控制发光装置的控制装置。 所述控制装置包括:光计量单元,被配置为从多个测光区域获取各自的测光值。 控制装置还包括校正单元,其被配置为基于目标区域的测光值和周边的测光区域的测光值之间的比较结果来校正关于目标区域的测光值的信息 所述多个测光区域中的目标区域,所述结果由所述光计量单元获取,从而允许所述发光装置执行预闪光。 此外,提供了一种计算单元,其被配置为基于由校正单元校正的关于测光值的信息来计算发光装置的主发光量。
    • 63. 发明申请
    • CLOCK GENERATION CIRCUIT AND INTEGRATED CIRCUIT
    • 时钟发生电路和集成电路
    • US20110210778A1
    • 2011-09-01
    • US13104771
    • 2011-05-10
    • Daisuke Yoshida
    • Daisuke Yoshida
    • H03H11/16
    • H03K5/133H03K5/1515H03K2005/00039H03K2005/00202H03L7/0805H03L7/0812H03L7/0995
    • A clock generation circuit comprises: a first generation unit; a second generation unit; and a control unit that, using a plurality of third delay elements that respectively have a propagation delay time that correlates with the propagation delay time of a first delay element, and correlates with the propagation delay time of a second delay element, generates a control signal for controlling the third delay elements such that a total of propagation delay times of the plurality of third delay elements corresponds to a target value depending on a cycle of the external clock, and controls the propagation delay time of the first delay element, the propagation delay time of the second delay element, and the propagation delay times of the third delay elements using the control signal.
    • 时钟发生电路包括:第一代单元; 第二代单位; 以及控制单元,使用分别具有与第一延迟元件的传播延迟时间相关的传播延迟时间并与第二延迟元件的传播延迟时间相关联的多个第三延迟元件,生成控制信号 用于控制第三延迟元件,使得多个第三延迟元件的传播延迟时间的总和对应于取决于外部时钟的周期的目标值,并且控制第一延迟元件的传播延迟时间,传播延迟 第二延迟元件的时间,以及使用控制信号的第三延迟元件的传播延迟时间。
    • 64. 发明授权
    • Clock generation circuit and integrated circuit
    • 时钟发生电路和集成电路
    • US07952409B2
    • 2011-05-31
    • US12606025
    • 2009-10-26
    • Daisuke Yoshida
    • Daisuke Yoshida
    • H03H11/16
    • H03K5/133H03K5/1515H03K2005/00039H03K2005/00202H03L7/0805H03L7/0812H03L7/0995
    • A clock generation circuit comprises: a first generation unit; a second generation unit; and a control unit that, using a plurality of third delay elements that respectively have a propagation delay time that correlates with the propagation delay time of a first delay element, and correlates with the propagation delay time of a second delay element, generates a control signal for controlling the third delay elements such that a total of propagation delay times of the plurality of third delay elements corresponds to a target value depending on a cycle of the external clock, and controls the propagation delay time of the first delay element, the propagation delay time of the second delay element, and the propagation delay times of the third delay elements using the control signal.
    • 时钟发生电路包括:第一代单元; 第二代单位; 以及控制单元,使用分别具有与第一延迟元件的传播延迟时间相关的传播延迟时间并与第二延迟元件的传播延迟时间相关联的多个第三延迟元件,生成控制信号 用于控制第三延迟元件,使得多个第三延迟元件的传播延迟时间的总和对应于取决于外部时钟的周期的目标值,并且控制第一延迟元件的传播延迟时间,传播延迟 第二延迟元件的时间,以及使用控制信号的第三延迟元件的传播延迟时间。
    • 65. 发明申请
    • IMAGE SIGNAL PROCESSING APPARATUS, IMAGE SIGNAL PROCESSING METHOD AND CAMERA USING THE IMAGE SIGNAL PROCESSING APPARATUS
    • 图像信号处理装置,图像信号处理方法和使用图像信号处理装置的相机
    • US20100231762A1
    • 2010-09-16
    • US12783323
    • 2010-05-19
    • Takahiro ShiraiDaisuke Yoshida
    • Takahiro ShiraiDaisuke Yoshida
    • H04N9/64
    • H04N5/3658
    • When clamping a signal from a solid state image sensor, float of an optical black pixel output due to incoming of infrared light avoids a malfunction of a clamp from occurring. When clamping a signal from the solid state image sensor, the difference between the optical black pixel output and a clamp target level is output as a difference output, the difference output is compared with a comparison level to integrate the number of times larger than the comparison level every horizontal line. When the number of times is equal to or more than a certain rate (⅔) from the number of optical black pixels on the horizontal line, an optical black float state is determined and clamping operation is performed in accordance with a held value immediately before.
    • 当夹持来自固态图像传感器的信号时,由于红外光的入射而导致的光学黑色像素的浮动避免了夹具的故障发生。 当从固态图像传感器夹紧信号时,输出光学黑色像素输出和钳位目标电平之间的差作为差分输出,将差分输出与比较电平进行比较,以将比较大于比较的次数 水平每一行。 当从水平线上的光学黑色像素的数量等于或大于一定速率(⅔)时,确定光学黑色浮动状态,并且根据紧接着的保持值执行夹紧操作。
    • 66. 发明申请
    • INTEGRATED CIRCUIT DEVICE AND IMAGING APPARATUS USING INTEGRATED CIRCUIT DEVICE
    • 集成电路设备和使用集成电路设备的成像设备
    • US20090159784A1
    • 2009-06-25
    • US12339169
    • 2008-12-19
    • Daisuke KobayashiDaisuke Yoshida
    • Daisuke KobayashiDaisuke Yoshida
    • H01L27/00H03F1/00H03F3/04H03F3/16
    • H03F3/08H04N5/32H04N5/357H04N5/3742H04N5/378
    • An integrated circuit device of the present invention includes a plurality of signal processing circuits classified into a plurality of groups, each signal processing circuit including an amplifier circuit for amplifying an input electric signal and a bias circuit having an input terminal connected electrically to a bias source and supplying a bias input terminal of the amplifier circuit with an operation bias for an amplifying operation of the amplifier circuit; and a plurality of connection wirings arranged each for each of the groups separately, such that the input terminals of the bias circuits of the signal processing circuits in one of the groups are commonly connected through the connection wirings. This provides an integrated circuit device suppressing the lowering of an image quality in consideration of enabling lower power consumption, a low noise characteristic, and high integration, and an imaging apparatus using the integrated circuit.
    • 本发明的集成电路装置包括分为多个组的多个信号处理电路,每个信号处理电路包括用于放大输入电信号的放大器电路和具有与偏压源电连接的输入端的偏置电路 以及向所述放大器电路的偏置输入端提供用于所述放大器电路的放大操作的操作偏置; 以及分别为每个组分别布置的多个连接配线,使得其中一个组中的信号处理电路的偏置电路的输入端子通过连接布线共同连接。 考虑到能够实现低功耗,低噪声特性和高集成度,以及使用集成电路的成像装置,提供了抑制图像质量降低的集成电路装置。
    • 68. 发明申请
    • Speech Synthesizing Apparatus
    • 语音合成装置
    • US20070203703A1
    • 2007-08-30
    • US10592071
    • 2005-03-29
    • Daisuke Yoshida
    • Daisuke Yoshida
    • G10L13/08
    • G10L13/10G10L13/07
    • A corpus-based speech synthesizing apparatus is provided which has a text analysis unit for analyzing a given sentence in text data and generating phonetic symbol data corresponding to the sentence; a prosody estimation unit for generating a prosodic parameter representing an accent and an intonation corresponding to each phonetic symbol data according to a preset prosodic knowledge base for accents and intonations; speech-unit extraction unit for extracting all the speech segment waveform data of a predetermined speech unit part from each speech data having the predetermined speech unit part closest to the prosodic parameter, based on a speech database which stores therein plural kinds of predetermined selectively prerecorded speech data only such that the speech database has a predetermined speech unit suitable for a specific application of the speech synthesizing apparatus; and a waveform connection unit for generating synthesized speech data by performing sequentially successive waveform connection of the speech segment waveform data groups such that the speech waveform of the speech segment waveform data groups continues, wherein the respective functional units, a data input unit, a speech conversion processing unit, and a speech speed conversion unit is added or removed as desired depending on a specific application and a scale of the apparatus.
    • 提供一种基于语料库的语音合成装置,其具有用于分析文本数据中的给定句子并产生与该句子相对应的语音符号数据的文本分析单元; 韵律估计单元,用于根据用于重音和语调的预设韵律知识库,生成表示对应于每个语音符号数据的重音和语调的韵律参数; 语音单元提取单元,用于从具有最接近韵律参数的预定语音单元部分的每个语音数据中提取预定语音单元部分的所有语音段波形数据,语音数据库存储多种预定的选择性预录制语音 数据,使得语音数据库具有适合语音合成装置的特定应用的预定语音单元; 以及波形连接单元,用于通过执行语音段波形数据组的顺序连续波形连接来产生合成语音数据,使得语音段波形数据组的语音波形继续,其中各个功能单元,数据输入单元,语音 转换处理单元和语音速度转换单元根据设备的具体应用和比例根据需要被添加或移除。
    • 69. 发明申请
    • Video encoding device
    • 视频编码设备
    • US20070047919A1
    • 2007-03-01
    • US11502591
    • 2006-08-09
    • Daisuke YoshidaKeisuke Inata
    • Daisuke YoshidaKeisuke Inata
    • H04N7/26
    • H04N19/61
    • A video encoding device capable of recording a plurality of videos at the same time is provided. It is a device capable of performing simultaneous compression encoding and recording of programs of at least one or more channels selected by using, for example, a video encoding method such as an MPEG-2 format, comprises an antenna, a tuner unit, a synchronizing signal generating unit, a recording channel control unit, a multichannel encoder, a recording unit, a monitor, a loudspeaker, a GUI and an overall control unit, and controls the recording channel control unit so that the encoding processing by the multichannel encoder is decreased.
    • 提供能够同时记录多个视频的视频编码装置。 它是能够对通过使用诸如MPEG-2格式的视频编码方法选择的至少一个或多个频道的程序进行同时压缩编码和记录的装置,包括天线,调谐器单元,同步 信号发生单元,记录通道控制单元,多通道编码器,记录单元,监视器,扬声器,GUI和总体控制单元,并且控制记录通道控制单元,使得多通道编码器的编码处理减少 。