专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20140161349A1 STRAIGHT LINE DETECTION APPARATUS AND STRAIGHT LINE DETECTION METHOD 有权
标题翻译：直线检测装置和直线检测方法
公开(公告)号：US20140161349A1
公开(公告)日：2014-06-12
申请号：US14232803
申请日：2012-07-06
申请人： Hiromu Hasegawa
发明人： Hiromu Hasegawa
IPC分类号： G06K9/46 , G06T11/00
CPC分类号： G06K9/4633 , G06T7/13 , G06T11/001 , G06T2207/20061
摘要： To detect a straight line using the Hough transform taking into consideration not only the number of points but also other properties of the straight line, the Hough transform unit performs a Hough transform on contour-enhanced binary image data. The Hough table stores a count after the Hough transform. The adjustment unit adjusts the count. The straight line detection unit detects a straight line based on the adjusted count. Additionally, to detect a straight line, independent of its direction or location in the image, for each straight line in the binary image data, the straight line calculation unit determines the intersections where that straight line cuts up the binary image data to calculate the intersection distance. The normalization unit divides the count stored in the Hough table by the intersection distance to normalize the count. The straight line detection unit detects a straight line based on the normalized count.
摘要翻译：为了使用霍夫变换来检测直线，不仅考虑点的数量，而且考虑到直线的其他属性，霍夫变换单元对轮廓增强的二进制图像数据执行霍夫变换。霍夫表在霍夫变换后存储一个计数。调整单元调整计数。直线检测单元基于经调整的计数检测直线。另外，为了检测独立于图像中的方向或位置的直线，对于二进制图像数据中的每条直线，直线计算单元确定该直线切割二进制图像数据以计算交点的交点距离。归一化单元将存储在霍夫表中的计数除以交叉距离以使计数正常化。直线检测单元基于归一化计数检测直线。

62. 发明授权

US08619864B2 Transcoding/encoding with code amount adjustment and stuffing bits 有权
标题翻译：用代码量调整和填充位的转码/编码
公开(公告)号：US08619864B2
公开(公告)日：2013-12-31
申请号：US12367658
申请日：2009-02-09
申请人： Makoto Saito , Hiromu Hasegawa
发明人： Makoto Saito , Hiromu Hasegawa
IPC分类号： H04N7/12 , H04N11/02
CPC分类号： H04N19/132 , H04N19/15 , H04N19/162 , H04N19/177 , H04N19/196 , H04N19/40
摘要： A reference differential value calculation part calculates a reference differential value by subtracting an accumulated value of the target amounts of codes from an accumulated value of the amounts of generated codes from the first period to the (n−1) period. A comparison part compares a cumulative differential value obtained by subtracting the cumulative amount of generated codes from the cumulative target amount of codes of the first to m-th picture frames in the n period with the reference differential value. If the cumulative differential value is larger than the reference differential value, stuffing bits are added to the m-th picture frame to be processed by the amount of codes obtained by subtracting the reference differential value from the cumulative differential value.
摘要翻译：参考差分值计算部分从第一周期到第（n-1）个周期的生成代码量的累计值中减去目标代码量的累加值来计算参考差分值。比较部分将通过从n个周期中的第一至第m个图像帧的累积目标量的累加量减去生成的代码获得的累积差分值与参考差分值进行比较。如果累积微分值大于参考差分值，则将填充比特添加到通过从累积微分值减去参考差分值而获得的代码量来处理的第m个图像帧。

63. 发明申请

US20130315266A1 SNR IMPROVEMENT CIRCUIT, SYNCHRONIZATION INFORMATION DETECTION CIRCUIT, COMMUNICATION DEVICE, SNR IMPROVEMENT METHOD, AND SYNCHRONIZATION INFORMATION DETECTION METHOD 有权
标题翻译： SNR改进电路，同步信息检测电路，通信设备，SNR改进方法和同步信息检测方法
公开(公告)号：US20130315266A1
公开(公告)日：2013-11-28
申请号：US13983924
申请日：2012-01-20
申请人： Handa Chen
发明人： Handa Chen
IPC分类号： H04L7/00
CPC分类号： H04L7/0041 , H04L7/042 , H04L27/2656 , H04L27/2675 , H04L27/2692
摘要： A technique capable of improving a packet catch rate when applied to a communication device, for example. An SNR improvement circuit for improving an SNR of an input signal includes a delay unit for delaying the input signal to generate one or more delay signals, and an adder for adding the one or more delay signals and the input signal before being delayed. The input signal contains a periodic signal in which the same signal is repeated a predetermined number of times with a predetermined period. The delay unit generates the one or more delay signals with delay time which is α times (α is a natural number, and is set at different values with respect to two or more delay signals) longer than the predetermined period.
摘要翻译：例如，当应用于通信设备时能够提高分组捕获速率的技术。用于改善输入信号的SNR的SNR改善电路包括用于延迟输入信号以产生一个或多个延迟信号的延迟单元，以及用于在延迟之前将一个或多个延迟信号和输入信号相加的加法器。输入信号包含周期信号，其中相同的信号以预定的周期重复预定次数。延迟单元产生一个或多个延迟信号，其延迟时间为α倍（α为自然数，并且相对于两个或多个延迟信号被设置为比预定周期长的不同值）。

64. 发明授权

US08548046B2 Transcoder 有权
标题翻译：转码器
公开(公告)号：US08548046B2
公开(公告)日：2013-10-01
申请号：US12394513
申请日：2009-02-27
申请人： Makoto Saito , Hiromu Hasegawa , Miyuki Yanagida
发明人： Makoto Saito , Hiromu Hasegawa , Miyuki Yanagida
IPC分类号： H04N7/26 , H04N7/12 , H04N7/46 , H04B1/66 , H04N7/50 , H04N7/32
CPC分类号： H04N19/40 , H04N19/115 , H04N19/126 , H04N19/139 , H04N19/14 , H04N19/149 , H04N19/172 , H04N19/177 , H04N19/179 , H04N19/192 , H04N19/61
摘要： A category setting part sets a type of a decoded image based on characteristics of the decoded image which are fineness of the decoded image and an intensity of movement of the decoded image. A code amount setting part sets a target code amount of an output image based on the type of the decoded image. A quantization step value setting part sets a quantization step value of the output image based on the target code amount of the output image. A transcoder can set the target code amount of the output image depending on fineness of the decoded image. The transcoder can distribute the target code amount of the output image to a reference image and a predicted image depending on the intensity of movement of the decoded image.
摘要翻译：类别设定部根据作为解码图像的细度的解码图像的特性和解码图像的移动强度来设定解码图像的种类。代码量设定部根据解码图像的种类来设定输出图像的目标代码量。量化步长值设定部根据输出图像的目标码量设定输出图像的量化步长值。代码转换器可以根据解码图像的细度来设置输出图像的目标代码量。代码转换器可以根据解码图像的移动强度将输出图像的目标代码量分配给参考图像和预测图像。

65. 发明申请

US20130235235A1 DATA TRANSFER APPARATUS AND DATA TRANSFER METHOD 有权
标题翻译：数据传输设备和数据传输方法
公开(公告)号：US20130235235A1
公开(公告)日：2013-09-12
申请号：US13785234
申请日：2013-03-05
申请人： MEGACHIPS CORPORATION
发明人： Kazuma TAKAHASHI
IPC分类号： H04N5/217
CPC分类号： H04N5/2173 , H04N5/3572
摘要： A data transfer apparatus includes a cache memory having a storing portion for writing and reading data at a higher speed than an image data storing portion which stores image data GD of an input image, and data transfer request means for outputting, to the cache memory, a transfer request for image data in a certain region of the input image. The cache memory reads unstored image data from the image data storing portion beyond a reading region corresponding to a transfer request every pixel row if image data in a pixel row included in the reading region is not stored in the storing portion of the cache memory. Moreover, the data transfer request means sequentially gives, in arrangement order in a horizontal direction of an input image, a transfer request for image data in each of reading regions arranged in the horizontal direction.
摘要翻译：数据传送装置包括：高速缓存存储器，具有用于以比存储输入图像的图像数据GD的图像数据存储部分更高的速度写入和读取数据的存储部分;以及数据传送请求装置，对输入图像的特定区域中的图像数据的传送请求。如果读取区域中包括的像素行中的图像数据未被存储在高速缓冲存储器的存储部分中，则高速缓冲存储器从每个像素行读取与图像数据存储部分相对应的读取区域的未分配图像数据。此外，数据传送请求装置按照排列顺序在输入图像的水平方向上顺序地给出沿水平方向布置的每个读取区域中的图像数据的传送请求。

66. 发明授权

US08515210B2 Image processing method and image processing device 有权
标题翻译：图像处理方法及图像处理装置
公开(公告)号：US08515210B2
公开(公告)日：2013-08-20
申请号：US13176430
申请日：2011-07-05
申请人： Hiromu Hasegawa , Yusuke Nara
发明人： Hiromu Hasegawa , Yusuke Nara
IPC分类号： G06K9/20
CPC分类号： H04N9/045 , H04N2209/046
摘要： An imaging device made of a single-chip type including a RGB Bayer pattern color filter is where pixel signals outputted from the imaging device are inputted through a signal processing part to an image processing part. A correlation judgment part judges a correlation between the pixel signals, and an interpolation processing part performs a pixel interpolation process based on a correlation result. Thus, each pixel signal becomes a perfect signal having all R, G and B color components. Filter factors for a filter are determined based on the correlation result, and a filtering process is performed on the pixel signals subjected to the pixel interpolation.
摘要翻译：由包括RGB拜耳图案彩色滤光片的单片式制成的成像装置是从成像装置输出的像素信号通过信号处理部分输入到图像处理部分。相关判断部判断像素信号之间的相关性，内插处理部根据相关结果进行像素内插处理。因此，每个像素信号变成具有所有R，G和B颜色分量的完美信号。基于相关结果确定滤波器的滤波因子，并且对经过像素插值的像素信号执行滤波处理。

67. 发明授权

US08514955B2 Communication system, data transmitter, and data receiver capable of detecting incorrect receipt of data 有权
标题翻译：通信系统，数据发送器和能够检测数据不正确接收的数据接收器
公开(公告)号：US08514955B2
公开(公告)日：2013-08-20
申请号：US12659408
申请日：2010-03-08
申请人： Ryuichi Moriizumi
发明人： Ryuichi Moriizumi
IPC分类号： H04L27/28
CPC分类号： H04L7/0091 , G01R31/31715 , G01R31/3187 , H04L1/0061 , H04L2007/045
摘要： A transmitter cyclic pattern having a pattern length of N bits is generated and converted into an M-bit transmitter parallel data stream, where N≠M. A bit-sequence altered transmitter parallel data stream is generated by performing a transmitter altering process, converted into a serial data and transmitted together with a clock signal. The serial data is received and converted into an M-bit receiver parallel data stream, and a bit-sequence restored parallel data stream is generated by performing a process opposite to the transmitter altering process. A receiver cyclic pattern is generated by using bits in the bit-sequence restored parallel data stream and converted into an M-bit reference parallel data stream, and a bit-sequence altered reference parallel data stream is generated by performing a process same as the transmitter altering process and compared with the received parallel data to test if the data is correctly received.
摘要翻译：产生具有N比特的模式长度的发射机循环模式，并将其转换为M比特发射机并行数据流，其中N≤M。通过执行发射机改变处理，转换成串行数据并与时钟信号一起传输，产生位序列改变的发射机并行数据流。串行数据被接收并转换成M位接收器并行数据流，并且通过执行与发送器改变处理相反的处理来生成比特序列恢复的并行数据流。通过使用比特序列恢复的并行数据流中的比特来生成接收机循环模式并将其转换成M比特参考并行数据流，并且通过执行与发射机相同的处理来生成比特序列改变的参考并行数据流更改流程并与收到的并行数据进行比较，以测试数据是否正确接收。

68. 发明授权

US08504897B2 Memory controller 有权
标题翻译：内存控制器
公开(公告)号：US08504897B2
公开(公告)日：2013-08-06
申请号：US12120489
申请日：2008-05-14
申请人： Masayuki Imagawa , Tetsuo Furuichi
发明人： Masayuki Imagawa , Tetsuo Furuichi
IPC分类号： G11C29/00
CPC分类号： G06F11/1016
摘要： A memory controller carries out error detection on a wide range of area of a memory cell array, which includes not only readout addresses but also non-readout addresses. Thus, by carrying out error detection at an address at which an error occurs without accessing the address for readout, it is possible to detect occurrence of an error at the address. Accordingly, it is possible to prevent a “read disturb phenomenon” in which repetition of access to a readout address for readout may probably cause an error at a non-readout address other than the readout address.
摘要翻译：存储器控制器在存储单元阵列的宽范围区域上执行错误检测，其不仅包括读出地址，而且包括非读出地址。因此，通过在发生错误的地址进行错误检测而不访问用于读出的地址，可以检测到地址处的错误的发生。因此，可以防止读出读出地址的重复访问可能在非读出地址以外的读出地址引起错误的“读取干扰现象”。

69. 发明授权

US08494293B2 Image processor 有权
标题翻译：图像处理器
公开(公告)号：US08494293B2
公开(公告)日：2013-07-23
申请号：US13153913
申请日：2011-06-06
申请人： Yusuke Mizuno , Yujiro Tani
发明人： Yusuke Mizuno , Yujiro Tani
IPC分类号： G06K9/36
CPC分类号： H04N19/436 , H04N19/60
摘要： The image processor 1 includes a frequency transform unit 12, an encoding unit 15, and a memory 4. The encoding unit 15 includes a DC processing unit 31 that generates a direct-current stream, an LP processing unit 32 that generates a low-frequency stream, an HP processing unit 33 that generates an upper high-frequency stream and a lower high-frequency stream, and an output unit 34 having output ports 41 to 44 to output the direct-current stream, the low-frequency stream, the upper high-frequency stream, and the lower high-frequency stream to the memory 4.
摘要翻译：图像处理器1包括频率变换单元12，编码单元15和存储器4.编码单元15包括生成直流流的DC处理单元31，生成低频的LP处理单元32 流，产生上高频流和下高频流的HP处理单元33以及具有输出端口41至44以输出直流流，低频流，上位流的输出单元34的输出单元34 高频流，低频流到存储器4。

70. 发明授权

US08381023B2 Memory system and computer system 有权
标题翻译：内存系统和计算机系统
公开(公告)号：US08381023B2
公开(公告)日：2013-02-19
申请号：US12646349
申请日：2009-12-23
申请人： Shinji Tanaka
发明人： Shinji Tanaka
IPC分类号： G06F11/00
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7202
摘要： A memory system according to the present invention includes, in addition to an computing device, a plurality of first blocks that are provided to store information including user information, and first physical addresses not overlapping one another are assigned to, respectively, and a plurality of second blocks that are provided to store first physical addresses of initial defect blocks out of the plurality of first blocks, respectively, wherein the computing device finds the first physical address corresponding a inputted given logical address, based on a given mirror logical address corresponding to the given logical address, and information stored in the second blocks.
摘要翻译：根据本发明的存储器系统除了计算设备之外还包括多个第一块，被提供用于存储包括用户信息的信息以及彼此不重叠的第一物理地址分别被分配给多个第二块，分别用于存储多个第一块中的初始缺陷块的第一物理地址，其中，所述计算设备基于与所述第一块对应的给定镜像逻辑地址，找到与输入的给定逻辑地址对应的第一物理地址给定的逻辑地址和存储在第二个块中的信息。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式