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61. 发明授权

US5396452A Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US5396452A
公开(公告)日：1995-03-07
申请号：US86222
申请日：1993-07-02
申请人： Sven E. Wahlstrom
发明人： Sven E. Wahlstrom
IPC分类号： G11C11/405 , G11C11/4074 , G11C11/4091 , G11C11/4096 , G11C11/4099 , G11C11/24
CPC分类号： G11C11/405 , G11C11/4074 , G11C11/4091 , G11C11/4096 , G11C11/4099
摘要： A dynamic random access memory. The memory includes a write transistor N3 and a read transistor N2. In a preferred embodiment the write transistor has a threshold level higher than the read transistor. A sense amplifier senses and amplifies a difference in voltage between a bit line and a sense node that is developed when the read transistor permits or does not permit current to flow between ground an a bit line. Associated semiconductor device structures and fabrication techniques are also disclosed.
摘要翻译：动态随机存取存储器。存储器包括写晶体管N3和读晶体管N2。在优选实施例中，写入晶体管具有高于读取晶体管的阈值电平。读出放大器感测并放大当读取晶体管允许或不允许电流在位线之间在地之间流动时产生的位线和感测节点之间的电压差。还公开了相关的半导体器件结构和制造技术。

62. 发明授权

US5289421A Dynamic random access memory with low noise characteristics 失效
标题翻译：具有低噪声特性的动态随机存取存储器
公开(公告)号：US5289421A
公开(公告)日：1994-02-22
申请号：US665261
申请日：1991-03-05
申请人： Jin-Hyo Lee , Kyu-Hong Lee
发明人： Jin-Hyo Lee , Kyu-Hong Lee
IPC分类号： G11C11/401 , G11C11/404 , G11C11/4099 , H01L21/8229 , H01L27/102 , G11C7/02
CPC分类号： G11C11/404 , G11C11/4099
摘要： A dynamic random access memory (DRAM) with low noise characteristics comprises a plurality of memory cells each consisting of a pair of reference memory cells respectively arranged between a word line and a pair of adjacent bit lines. The reference memory cells store signals of opposite levels corresponding to one bit of information. Each of the reference memory cells consists of a capacitor and switching transistor. One end of the capacitor is connected to the collector of the transistor. The other end of the capacitor is connected to one of the pair of bit lines adjacent thereto. The base of the transistor is connected to the word line, and the emitter of the transistor is completed to receive a reference voltage.
摘要翻译：具有低噪声特性的动态随机存取存储器（DRAM）包括多个存储单元，每个存储单元由分别布置在字线和一对相邻位线之间的一对参考存储单元构成。参考存储单元存储对应于一位信息的相反电平的信号。每个参考存储单元由电容器和开关晶体管组成。电容器的一端连接到晶体管的集电极。电容器的另一端连接到与其相邻的一对位线之一。晶体管的基极连接到字线，并且晶体管的发射极完成以接收参考电压。

63. 发明授权

US5031153A MOS semiconductor memory device having sense control circuitry simplified 失效
标题翻译：具有简化的感测控制电路的MOS半导体存储器件
公开(公告)号：US5031153A
公开(公告)日：1991-07-09
申请号：US449562
申请日：1989-12-12
申请人： Junichi Suyama
发明人： Junichi Suyama
IPC分类号： G11C11/401 , G11C7/14 , G11C11/407 , G11C11/409 , G11C11/4091 , G11C11/4099
CPC分类号： G11C11/4091 , G11C11/4099 , G11C7/14
摘要： An MOS semiconductor memory device includes memory cell matrices. Each matrix is constituted with memory cells and noise cancellers. Each memory cell is connected, at an intersection between a pair of bit lines and a word line, between either one of the bit lines and the word line. The word line controls read and write operations of the memory cell. The noise canceller is connected, at an intersection between a pair of bit lines and a dummy word line, between either one of the bit lines and the dummy word line. The dummy word line enables the noise canceller. The memory cell matrices form groups of memory cells into which the cells are grouped in accordance wtih addresses. The dummy word line and the word line have substantially identical characteristics. The dummy word line possesses parasitic resistance and capacitance to delay by a first predetermined period of time a signal to enable the noise canceller. The memory device further includes sense amplifier circuits connected between the pair of bit lines of the memory cell matrices for amplifying a potential difference between the bit lines in response to an enable signal, and a sense control circuit connected to the dummy word lines and the sense amplifier circuits to be operative in a read or write operation of the memory cell for selectively enabling related sense amplifier circuits in response to a signal delayed by a dummy word line of selected ones of the memory cell matrices.
摘要翻译： MOS半导体存储器件包括存储单元矩阵。每个矩阵由存储器单元和噪声消除器构成。每个存储器单元在位线和字线中的任一个之间的一对位线和字线之间的交叉点处连接。字线控制存储单元的读写操作。噪声消除器在位线和哑字线之间的一对位线和虚拟字线之间的交叉点处连接。虚拟字线使噪声消除器。存储单元矩阵形成存储单元组，单元根据地址分组到其中。虚拟字线和字线具有基本相同的特性。虚拟字线具有寄生电阻和电容，以延迟第一预定时间段以产生噪声消除器的信号。存储装置还包括连接在存储单元矩阵的一对位线之间的读出放大器电路，用于响应于使能信号放大位线之间的电位差，以及连接到虚拟字线和感测的读出控制电路放大器电路在存储器单元的读取或写入操作中工作，用于响应于被选择的存储单元矩阵的虚拟字线延迟的信号选择性地使能相关读出放大器电路。

64. 发明授权

US5001669A Semiconductor memory circuit having dummy cells connected to twisted bit lines 失效
标题翻译：半导体存储器电路具有连接到扭曲位线的虚设单元
公开(公告)号：US5001669A
公开(公告)日：1991-03-19
申请号：US385727
申请日：1989-07-26
申请人： Shizuo Cho , Masaru Uesugi
发明人： Shizuo Cho , Masaru Uesugi
IPC分类号： G11C11/401 , G11C7/14 , G11C7/18 , G11C11/4099
CPC分类号： G11C7/14 , G11C11/4099 , G11C7/18
摘要： A semiconductor memory circuit includes a plurality of bit line pairs each having intersecting portions where the paired bit lines intersect each other, and a plurality of pairs of memory word lines intersecting the bit lines in a direction substantially perpendicular to the bit lines. A plurality of memory cells are individually connected to the memory word lines and bit lines at intersections of one of the memory word lines of the individual memory word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired memory word lines and the other of the paired bit lines for storing charges each being associated with data to be sorted. A pair of dummy word lines are interposed between the intersecting portions of the bit lines and intersect the bit line pairs in a direction substantially perpendicular to the bit line pairs. A plurality of dummy cells are individually connected between the dummy word line pairs and the bit line pairs at intersections of one of the dummy word lines of the individual word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired dummy word lines and the other of the paired bit lines.
摘要翻译：半导体存储器电路包括多个位线对，每个位线对具有成对的位线相交的相交部分，以及与位线基本上垂直于位线的方向相交的多对存储器字线。多个存储器单元分别连接到各个存储字线对的一个存储字线和各位线对中的一个位线和另一个的交叉点之间的交叉处的存储器字线和位线的配对存储器字线和用于存储每个与要排序的数据相关联的电荷的成对位线中的另一个。一对虚拟字线插入在位线的相交部分之间，并且在与位线对基本垂直的方向上与位线对相交。多个虚拟单元分别连接在虚拟字线对和位线对之间，在各个字线对之间的一个虚拟字线和各个位线对的位线之一的交点处和配对的虚拟字线中的另一个和配对的位线中的另一个。

65. 发明授权

US4811290A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4811290A
公开(公告)日：1989-03-07
申请号：US31615
申请日：1987-03-30
申请人： Shigeyoshi Watanabe
发明人： Shigeyoshi Watanabe
IPC分类号： H01L27/10 , G11C11/4091 , G11C11/4099 , H01L21/8242 , H01L27/108 , G11C11/24 , G11C7/00
CPC分类号： G11C11/4099 , G11C11/4091
摘要： A dynamic random access memory including a sense amplifier having MOSFETs, which constitute a flip-flop, and an activating MOSFET. A memory cell includes a switching MOSFET and a capacitor having a grooved structure. A dummy cell includes a switching MOSFET and capacitor having a planar structure. The activating MOSFET has its gate coupled to a gate bias generator, which comprises a reference capacitor group consisting of planar type capacitors having a nearly constant capacitance, irrespective of the influence of process parameters, and a monitoring capacitor group consisting of capacitors having the same grooved structure and the same capacitance as the memory cell capacitor. The reference capacitor group, and the monitoring capacitor group are pre-charged. When the sensing operation starts, the reference capacitor group and the monitoring capacitor group are short-circuited, so that a charge reallocation is executed between these groups. When a word line driver functions, the gate of the switching MOSFET of the memory cell is open, thus transferring data of the memory cell capacitor and dummy cell capacitor onto bit line BL and BL. The voltage of the node between the reference and monitoring capacitor groups, which are short-circuited, is applied to the gate of the activating MOSFET of the sense amplifier after a predetermined time delay.
摘要翻译：动态随机存取存储器包括构成触发器的具有MOSFET的读出放大器和激活MOSFET。存储单元包括开关MOSFET和具有沟槽结构的电容器。虚设单元包括具有平面结构的开关MOSFET和电容器。激活MOSFET的栅极耦合到栅极偏置发生器，其包括由具有几乎恒定电容的平面型电容器组成的参考电容器组，与工艺参数的影响无关，以及由具有相同沟槽的电容器组成的监测电容器组结构和与存储单元电容器相同的电容。参考电容器组和监控电容组预充电。当感测操作开始时，参考电容器组和监视电容器组短路，从而在这些组之间执行电荷重新分配。当字线驱动器工作时，存储单元的开关MOSFET的栅极断开，从而将存储单元电容器和虚设单元电容器的数据传输到位线和上升沿B和BL。在预定的时间延迟之后，将被短路的基准电压和监视电容器组之间的节点的电压施加到读出放大器的激活MOSFET的栅极。

66. 发明授权

US4792928A Semiconductor memory circuit with control of bit line voltage balancing 失效
标题翻译：具有控制位线电压平衡的半导体存储电路
公开(公告)号：US4792928A
公开(公告)日：1988-12-20
申请号：US18467
申请日：1987-02-25
申请人： Youichi Tobita
发明人： Youichi Tobita
IPC分类号： G11C11/409 , G11C11/40 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/4094 , G11C11/4099 , G11C7/00 , G11C7/02
CPC分类号： G11C11/4099 , G11C11/4076 , G11C11/4094
摘要： A semiconductor memory circuit includes: a plurality of memory cell columns each comprising a plurality of memory cells connected to a bit line, at least a dummy cell connected to a bit line constituting a bit line pair with said bit line, a sense amplifier connected between said two bit lines, and at least a FET for balancing the voltages of said two bit lines; and a balance control circuit for detecting the termination of selection of a dummy word line which is provided for the control of the dummy cell and thereafter operating the FET.
摘要翻译：半导体存储器电路包括：多个存储单元列，每个存储单元列包括连接到位线的多个存储单元，至少连接到构成与所述位线的位线对的位线的虚拟单元，连接在所述两个位线，以及至少一个用于平衡所述两个位线的电压的FET; 以及平衡控制电路，用于检测为虚拟单元的控制提供的虚拟字线的选择的终止，然后操作该FET。

67. 发明授权

US4669065A Dynamic memory apparatus having a sense amplifier and a reference voltage connection circuit therefor 失效
标题翻译：具有读出放大器及其参考电压连接电路的动态存储装置
公开(公告)号：US4669065A
公开(公告)日：1987-05-26
申请号：US671425
申请日：1984-11-14
申请人： Akira Ohsawa
发明人： Akira Ohsawa
IPC分类号： G11C11/401 , G11C7/14 , G11C11/4099 , G11C11/24
CPC分类号： G11C7/14 , G11C11/4099
摘要： A memory apparatus has a dummy cell comprising two sets of series connections of MOS transistors and capacitors, respectively, connected to a pair of bit lines, which are connected to a sense amplifier of a flip-flop type, and a third MOS transistor having a source and a drain thereof connected between junction points of the MOS transistors and the capacitors of the dummy cell. The capacitors are charged at a high level potential and a low level potential, respectively, of the bit lines and then they are shorted to each other through the third MOS transistor so that they have a common potential of a middle potential level. The potential of the middle level can be supplied to a pair of input terminals to the flip-flop type sense amplifier as a reference potential signal. Thus, it is possible to assure a stable sensing operation by the sense amplifier which is free from an influence of a change in the potential of a substrate of the memory apparatus.
摘要翻译：一种存储装置具有一个虚拟单元，包括分别连接到一对位线的MOS晶体管和电容器的两组串联连接，这两个位线连接到触发器类型的读出放大器，第三MOS晶体管具有源极和漏极连接在MOS晶体管的接点和虚设电池的电容器之间。电容器分别以位线的高电平电位和低电平电位充电，然后它们通过第三MOS晶体管彼此短路，使得它们具有中间电位电平的公共电位。可以将中间电平的电位提供给作为参考电位信号的触发器型读出放大器的一对输入端。因此，可以通过读出放大器确保不受存储装置的基板的电位变化的影响的稳定的感测操作。

68. 发明授权

US4622655A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4622655A
公开(公告)日：1986-11-11
申请号：US607026
申请日：1984-05-04
申请人： Shunichi Suzuki
发明人： Shunichi Suzuki
IPC分类号： G11C11/409 , G11C11/4099 , G11C11/24
CPC分类号： G11C11/4099
摘要： A semiconductor memory has at least a pair of bit lines, a plurality of word lines crossing the pair of bit lines, a pair of dummy word lines crossing the pair of bit lines, memory cells arranged at intersections between the bit lines and the word lines, dummy cells arranged at intersections between any the bit lines and the dummy word lines, a sense amplifier connected to the pair of bit lines, and a means for equalizing the potentials of the pair of bit lines. Each of the memory cell has a transistor and a capacitor. Each dummy cell has the same construction as each memory cell. The pair of bit lines and dummy cell capacitors are electrically connected at a predetermined timing and are set at a third voltage, the corresponding dummy cell is disconnected from one of the bit line pair, to which a selected memory cell capacitor is connected. Subsequently, a voltage difference between voltages on the bit lines is detected.
摘要翻译：半导体存储器具有至少一对位线，与该对位线交叉的多条字线，与该对位线交叉的一对虚拟字线，位于位线和字线之间的交叉处的存储单元布置在任何位线和虚拟字线之间的交叉处的虚拟单元，连接到所述一对位线的读出放大器以及用于均衡所述一对位线的电位的装置。每个存储单元具有晶体管和电容器。每个虚拟单元具有与每个存储单元相同的结构。一对位线和虚设单元电容器以预定的定时电连接并被设置为第三电压，相应的虚设单元与连接所选存储单元电容器的位线对之一断开。随后，检测位线上的电压之间的电压差。

69. 发明授权

US4195357A Median spaced dummy cell layout for MOS random access memory 失效
标题翻译：用于MOS随机存取存储器的中间空间虚拟单元布局
公开(公告)号：US4195357A
公开(公告)日：1980-03-25
申请号：US915632
申请日：1978-06-15
申请人： Chang-Kiang Kuo , Shyh-Chang Tsaur
发明人： Chang-Kiang Kuo , Shyh-Chang Tsaur
IPC分类号： G11C11/404 , G11C11/4099 , G11C7/00
CPC分类号： G11C11/4099 , G11C11/404
摘要： A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with bistable sense amplifier circuits at the center of each column. A dummy cell is connected to each column line half and is addressed when a memory cell on the opposite side of the sense amplifier is addressed by one of the row lines. Time delay is made more equal by placing the dummy cells at about the center of each column line half. The signals on the column line halves from the dummy cell and from the selected memory cell will reach the sense amplifier at about the same time, on average.
摘要翻译： MOS集成电路类型的随机存取存储器件采用在每列的中心具有双稳态读出放大器电路的单晶体管存储单元的行和列阵列。虚拟单元连接到每个列线一半，并且当读出放大器的相对侧上的存储单元由行行之一寻址时被寻址。通过将虚拟单元放置在每个列线的中心的一半处使时间延迟更加相等。列线上的信号从虚拟单元中减半，并且所选择的存储单元平均大约在同一时间到达读出放大器。

70. 发明授权

US3760381A Stored charge memory detection circuit 失效
标题翻译：存储充电记忆检测电路
公开(公告)号：US3760381A
公开(公告)日：1973-09-18
申请号：US3760381D
申请日：1972-06-30
申请人： IBM
发明人： YAO Y
IPC分类号： G11C11/419 , G11C7/02 , G11C11/404 , G11C11/409 , G11C11/4091 , G11C11/4099 , G11C11/24 , G11C7/06
CPC分类号： G11C11/4099 , G11C11/404 , G11C11/4091
摘要： A sensing circuit which is responsive to binary information represented by the level of charge in a capacitor is disclosed. The circuit comprises a differential amplifier; the nodes of which are connected to bucket brigade sense amplifier arrangements which are in turn connected to bit lines to which a plurality of memory device which store information in the form of charge are connected. Each bit line portion connected to the bucket brigade sense amplifier represents half of a bit line to which a plurality of storage devices (such as a capacitor in series with an FET gate) are connected. Each half of the bit line is also connected to a reference capacitor via an actuable FET device or other stored charge memory device. Each of the bucket brigade sense amplifiers consists of an output capacitance which is connected in parallel with the bit line capacitances of each half of the bit line via an actuable FET device. A source of voltage for charging the bit line capacitances is connected to the bit line halves via an actuable FET device and is utilized to charge the bit line capacitance, the output capacitance and a reference capacitor of one of the bit line halves. In operation, both bit line halves are charged to some voltage which is usually equal to the voltage to which the capacitance of a selected memory cell can be charged. At the same time, a reference capacitor is charged to approximately one half the voltage to which the selected cell capacitance can be charged. If the reference capacitor is to be charged to half the voltage of a storage cell, the size of the reference capacitor should be equal to that of the storage capacitor. Another way of implementing the reference capacitor is to use a reference capacitor half the size of a storage capacitor and discharge it completely each time before selecting a memory cell. If the memory cell capacitor is charged to full voltage (representing a binary ''''1'''') when the word line of the memory cell is activated for reading, no charge will flow from the bit line capacitance to the memory cell capacitance because both are at the same level. If the memory cell capacitance were empty (representing a binary ''''0'''') charge would flow from the bit line capacitance when reading occurred, filling the memory capacitor and reducing the bit line capacitor voltage by a small ion. When the bucket brigade circuit is actuated, no charge transfer occurs where the memory capacitor was full and a voltage approximately equal to the bit line charging voltage appears on one node of the differential amplifier. Where the memory capacitor was initially empty, charge transfer occurs to refill the bit line capacitance to its original level thereby depleting the output capacitance of charge and causing zero potential to be applied to one node of the differential amplifier. Simultaneously, with the appearance of the bit line charging voltage or zero at one node of the differential amplifier, a voltage equal to approximately half the bit line charging voltage appears at the other node of the differential amplifier. This results from the charging of the reference capacitance to one half the charging voltage. When reading of the reference capacitance occurs, charge from the bit line capacitance charges the reference capacitor up to its full value, depleting the bit line capacItance of an amount of charge equal to half the charge depleted from the opposite bit line capacitance when a memory cell storing a ''''0'''' is selected. When the bucket brigade sense amplifier is actuated, charge from the output capacitance thereof replenishes the bit line capacitance and leaves the output capacitance at a value of voltage approximately equal to one half of the charging voltage. In this manner, when a selected memory device associated with one half of a bit line is being read, the reference capacitance associated with the other half of the bit line is utilized to provide a voltage which is always the same regardless of the voltage on the selected device. The appropriate reference capacitor is selected by arranging the decoding such that when a memory device on one bit line half is selected, the reference capacitor on the other bit line half is always selected.
摘要翻译：公开了一种响应由电容器中的电荷电平表示的二进制信息的感测电路。电路包括差分放大器; 它们的节点被连接到桶旅读出放大器装置，这些装置又连接到以电荷形式存储信息的多个存储装置连接到的位线。每个位线部分连接到降压

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