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61. 发明授权

US5442308A Dynamic decoder circuit operative at low frequency clock signals without data destruction 失效
标题翻译：动态解码器电路在低频时钟信号下工作，无数据破坏
公开(公告)号：US5442308A
公开(公告)日：1995-08-15
申请号：US190477
申请日：1994-02-02
申请人： Hisashi Fujiwara
发明人： Hisashi Fujiwara
IPC分类号： G11C8/04 , G11C7/10 , G11C8/10 , G11C11/408 , G11C11/413 , G11C16/06 , G11C17/00 , H03M7/00 , H03K19/0948
CPC分类号： G11C7/1072 , G11C8/10 , H03M7/005
摘要： A dynamic decoder stores decoded signals in latch circuits for producing output signals, and the latch circuits are disabled after storing the decoded signals so that the output signals are free from undesirable level change of the decoded signals due to leakage between the dynamic decoding operations.
摘要翻译：动态解码器将解码信号存储在用于产生输出信号的锁存电路中，并且在存储解码信号之后锁存电路被禁用，使得输出信号由于动态解码操作之间的泄漏而没有不希望的电平改变。

62. 发明授权

US5434899A Phase clocked shift register with cross connecting between stages 失效
标题翻译：相位时钟移位寄存器，用于级间交叉连接
公开(公告)号：US5434899A
公开(公告)日：1995-07-18
申请号：US288793
申请日：1994-08-12
申请人： Ruquiya I. A. Huq , Sherman Weisbrod
发明人： Ruquiya I. A. Huq , Sherman Weisbrod
IPC分类号： G11C19/00 , G09G3/36 , G11C8/04 , G11C19/28 , H03K5/15
CPC分类号： G11C19/28 , G09G3/3674 , G11C8/04
摘要： A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. The input transistor switch charges a capacitance associated with a control electrode of a switched pull-up output transistor. The voltage in the capacitance conditions the output transistor for generating an output pulse when subsequently a clock signal occurs to the output transistor. A clamping transistor discharges the capacitance in a manner to prevent further generation of the output pulse when subsequent pulses of the clock signal occur. The clamping transistor is responsive to an output pulse of a stage downstream in the chain. An impedance that is developed at the control electrode is substantially higher after the clamping operation occurs and remain high for most of the vertical interval.
摘要翻译：用于扫描液晶显示器的移位寄存器包括级联级。给定级由形成在级联级链中的级上游的输出脉冲的输入晶体管开关形成。输入晶体管开关对与开关上拉输出晶体管的控制电极相关联的电容进行充电。当输出晶体管发生时钟信号时，电容中的电压使输出晶体管产生输出脉冲。钳位晶体管以这样的方式放电电容，以防止随后的时钟信号脉冲发生时进一步产生输出脉冲。钳位晶体管响应于链中下游的级的输出脉冲。在控制电极上产生的阻抗在钳位操作发生之后显着更高，并且在大部分垂直间隔中保持高电平。

63. 发明授权

US5377154A Multiple serial-access memory 失效
标题翻译：多个串行存取存储器
公开(公告)号：US5377154A
公开(公告)日：1994-12-27
申请号：US10645
申请日：1993-01-28
申请人： Atsushi Takasugi
发明人： Atsushi Takasugi
IPC分类号： G11C7/10 , G11C8/00 , G11C8/04
CPC分类号： G11C7/1006 , G11C7/1018
摘要： A serial access memory consists of two or more memory cell arrays fabricated as a single integrated circuit. A serial input port is provided for input of data to one of the memory cell arrays. Separate serial output ports are provided for output of data from each of the memory cell arrays. Data are transferred among the memory cell arrays in parallel form by one or more internal transfer circuits.
摘要翻译：串行访问存储器由两个或更多个作为单个集成电路制造的存储单元阵列组成。提供串行输入端口用于将数据输入到存储单元阵列之一。单独的串行输出端口用于从每个存储单元阵列输出数据。数据通过一个或多个内部传输电路以并行形式在存储单元阵列之间传送。

64. 发明授权

US5329484A Semiconductor memory circuit, semiconductor memory module using the same, and acoustic signal reproducing system 失效
标题翻译：半导体存储器电路，使用其的半导体存储器模块和声信号再现系统
公开(公告)号：US5329484A
公开(公告)日：1994-07-12
申请号：US71389
申请日：1993-06-02
申请人： Hideo Tsuiki
发明人： Hideo Tsuiki
IPC分类号： G11C5/00 , G10K15/02 , G11C7/16 , G11C8/04 , G11C27/00
CPC分类号： G11C8/04 , G10K15/02 , G11C7/16
摘要： A sequential access type memory medium of a large memory capacity is composed of a number of semiconductor memory modules, each including a semiconductor memory device and necessary peripheral circuits accommodated in a square package. The same number of terminals are provided on each of four sides of the square package. The terminals on the four sides are so wired that the same kind of signal is transferred through positionally corresponding terminals of four sides of the square package, and the terminals on one side are of a plug type and the terminals on the remaining three sides are of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines. In addition, positionally corresponding socket type terminals of three sides of each memory module are interconnected so as to interconnect the terminals for the same signal. Thus, a plurality of memory modules are interconnected in an arbitrary order and in arbitrary location with using no printed circuit board and with a high expandability, so that in each semiconductor memory module, an address signal is generated on the basis of the synchronous signal supplied from an external, and the synchronous signal is supplied to the just succeeding semiconductor memory circuit after the data reading of the first mentioned semiconductor memory circuit has been completed.
摘要翻译：具有大存储容量的顺序访问型存储介质由多个半导体存储器模块组成，每个半导体存储器模块包括半导体存储器件和容纳在正方形封装中的必要的外围电路。在方形包装的四个侧面上设置相同数量的端子。四边的端子是这样布线的，使得相同种类的信号通过方形封装的四边的位置相应的端子传送，一侧的端子是插头型的，其余三边的端子是插座型，可以与插头型端子配合并连接，以便互连相应的信号线。此外，每个存储器模块的三侧的位置对应的插座型端子互连，以便将相同信号的端子互连。因此，多个存储器模块以任意顺序和任意位置互连，不使用印刷电路板并且具有高可扩展性，使得在每个半导体存储器模块中，基于所提供的同步信号产生地址信号并且在首次提到的半导体存储器电路的数据读取已经完成之后，同步信号被提供给刚才的半导体存储器电路。

65. 发明授权

US5282166A Serial access memory comprising disconnecting circuit between serial bus lines and preamplifier 失效
标题翻译：串行存取存储器包括在串行总线和前置放大器之间断开电路
公开(公告)号：US5282166A
公开(公告)日：1994-01-25
申请号：US825214
申请日：1992-01-24
申请人： Atsushi Ozaki
发明人： Atsushi Ozaki
IPC分类号： G11C8/04 , G11C7/06 , G11C7/12 , G11C11/401 , G11C11/409 , G11C11/417 , G11C7/00
CPC分类号： G11C7/12 , G11C7/062 , G11C7/065
摘要： An improved serial access memory without erroneous reading where a faster reading operation is required. The serial access memory includes a disconnecting circuit connected between a serial bus line pair and a preamplifier. A data signal read out from a memory cell is provided to the preamplifier via the serial bus line pair. The disconnecting circuit electrically disconnects the serial bus line pair from the preamplifier after a predetermined time has elapsed since the preamplifier commences amplifying operation. An equalize circuit commences equalization of a next data signal right after the operation of the disconnecting circuit. Since the equalize timing of the serial bus line pair for reading the next data is made to commence earlier, proper reading operation can be realized even if the frequency of an externally applied serial out clock signal SOC is increased.
摘要翻译：改进的串行访问存储器，而不需要更快读取操作的错误读取。串行存取存储器包括连接在串行总线对和前置放大器之间的断开电路。从存储单元读出的数据信号通过串行总线对提供给前置放大器。在从前置放大器开始放大操作经过预定时间之后，断开电路将串行总线线对与前置放大器电气断开。均衡电路在断开电路的操作之后开始下一个数据信号的均衡。由于用于读取下一个数据的串行总线线对的均衡时间早于开始，因此即使外部施加的串行输出时钟信号SOC的频率增加，也可以实现适当的读取操作。

66. 发明授权

US5255242A Sequential memory 失效
标题翻译：顺序记忆
公开(公告)号：US5255242A
公开(公告)日：1993-10-19
申请号：US628316
申请日：1990-12-17
申请人： Morris D. Ward , Jy-Der Tai , Kenneth L. Williams
发明人： Morris D. Ward , Jy-Der Tai , Kenneth L. Williams
IPC分类号： G06F5/16 , G11C7/00 , G11C7/10 , G11C8/04
CPC分类号： G11C7/1042
摘要： A sequential memory (10) uses interleaved memories (12a-b) with associated output buffers (22a-b) accomplish high data rates. Data access control circuitry (18) and bank select circuitry (20) control the order in which the memory banks (12a-b) are written to and read from. Output buffer circuits (22a-b) allow a data word to be read instantaneously after it is written to the sequential memory (10).

67. 发明授权

US5166960A Parallel multi-phased a-Si shift register for fast addressing of an a-Si array 失效
标题翻译：并联多相a-Si移位寄存器，用于快速寻址a-Si阵列
公开(公告)号：US5166960A
公开(公告)日：1992-11-24
申请号：US871243
申请日：1992-04-20
申请人： Victor M. Da Costa
发明人： Victor M. Da Costa
IPC分类号： G11C19/00 , G11C8/04 , G11C19/28 , H03K19/173
CPC分类号： G11C8/04 , G11C19/28 , H03K19/1732
摘要： An improved shift register assembly having an integrated multi-phased dynamic shift register with a corresponding multi-phased driving buffer for addressing elements of an array. The shift register and buffer combination is used to select segments on the array having a common select line thus reducing the number of input lines needed to address such an array. Furthermore, the multi-phased operation of the shift register allows for faster operation than tyhat of a traditional shift register setup.
摘要翻译：一种改进的移位寄存器组件，其具有集成的多相动态移位寄存器，其具有用于寻址阵列元件的对应的多相驱动缓冲器。移位寄存器和缓冲器组合用于选择具有公共选择线的阵列上的段，从而减少了解决这种阵列所需的输入线的数量。此外，移位寄存器的多阶段操作允许比传统移位寄存器设置的tyhat更快的操作。

68. 发明授权

US5046051A Serial memory with address counter which can be preset using a multi-purpose input, and picture memory apparatus using same 失效
标题翻译：具有可以使用多功能输入预设的地址计数器的串行存储器和使用其的图像存储装置
公开(公告)号：US5046051A
公开(公告)日：1991-09-03
申请号：US269229
申请日：1988-11-09
申请人： Laurens Doornhein , Jeroen Kettenis
发明人： Laurens Doornhein , Jeroen Kettenis
IPC分类号： G11C19/00 , G11C5/06 , G11C8/04
CPC分类号： G11C5/066
摘要： A serial memory in which serial address input devices share a terminal with control signal input devices is suitable for the non-shifting storage of information and includes at least one address counter which receives address incrementation signals from a clock and which is suitable for receiving a preset address on the serial address input means.

69. 发明授权

US5016226A Apparatus for generating a data stream 失效
标题翻译：用于产生数据流的装置
公开(公告)号：US5016226A
公开(公告)日：1991-05-14
申请号：US269386
申请日：1988-11-09
申请人： Kiyokasu Hiwada , Nobuyuki Kasuga
发明人： Kiyokasu Hiwada , Nobuyuki Kasuga
IPC分类号： G06F12/04 , G06F12/06 , G11C8/04
CPC分类号： G11C8/04
摘要： In one embodiment of the invention, the selection of the number of the latches from which data is read can be changed dynamically during the generation of the data stream. The scanning of the latches can be stopped temporarily while the next set of data from the memory is stored in the latches, then resumed. For example, assume that n+1 number of banks are provided in the memory and that the selection of the number of the latches can be changed dynamically between n and n+1. Then, the possible length/period, N, of the data stream that can be generated would be:N=i*n+j*(n+1)where i and j are non-negative integers, and one of i or j is non-zero.In another embodiment of the present invention, the memory has m+n banks, and the latch group has m+n latches. The number of the latches from which data is read during each scanning cycle can be selected from the range n, n+1, . . . , n+m-1, n+m. Consequently, any data stream having a length or period which is a multiple of any of n, n+1, . . . , n+m-1, n+m can be generated.
摘要翻译：在本发明的一个实施例中，可以在数据流的生成期间动态地改变读取数据的锁存器的数量的选择。锁存器的扫描可以暂时停止，而存储器中的下一组数据存储在锁存器中，然后恢复。例如，假设在存储器中提供n + 1个存储体，并且可以在n和n + 1之间动态地改变锁存器的数量的选择。然后，可以生成的数据流的可能长度/周期N可以是：N = i * n + j *（n + 1）其中i和j是非负整数，i或j之一是非零。在本发明的另一实施例中，存储器具有m + n个存储体，并且锁存器组具有m + n个锁存器。在每个扫描周期中从中读取数据的锁存器的数量可以从范围n，n + 1，...中选择。。。，n + m-1，n + m。因此，具有长度或周期的任何数据流是n，n + 1，...中的任一个的倍数。。。，可以产生n + m-1，n + m。

70. 发明授权

US5005158A Redundancy for serial memory 失效
标题翻译：冗余串行存储器
公开(公告)号：US5005158A
公开(公告)日：1991-04-02
申请号：US464219
申请日：1990-01-12
申请人： David C. McClure , Mark A. Lysinger
发明人： David C. McClure , Mark A. Lysinger
IPC分类号： G11C8/04 , G11C29/00 , G11C29/04
CPC分类号： G11C29/86 , G11C8/04
摘要： A fault tolerant sequential memory includes primary and redundant memory rows (or columns) and primary and redundant shift registers. The redundant memory rows (or columns) and redundant shift registers are formed at the end of the serial chain. Each shift register of each primary and redundant memory block is interconnected with an independent, separately programmable multiplexer logic circuit. Each multiplexer logic circuit includes an independently programmable repair buffer for logically bypassing a defective primary memory block and associated shift registers within the primary memory array. Each redundant memory block includes a multiplexer logic circuit having an independently programmable repair buffer for logically enabling a redundant memory block and shift register at the end of the serial chain. Consequently, a faulty memory block, including its shift register and memory row (or column) is bypassed and is effectively removed from the shifting sequence. The redundant memory block, including a redundant shift register and a redundant row (or column), is inserted at the end of the shift register chain by opening a programmable fuse element.

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